[PATCH 22.11] net/mlx5: fix Tx metadata pattern template mismatch

[PATCH 22.11] net/mlx5: fix Tx metadata pattern template mismatch

[Shani Peretz]

When representor matching is disabled with dv_xmeta_en=4, the Tx metadata
copy flows use SQ (send queue) pattern matching, but the pattern template
was still configured to use ETH match-all pattern. This mismatch causes
hardware to reject the flows with error CQEs during port configuration.

This patch fixes the issue by using SQ-based pattern template
(flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all
template (flow_hw_create_tx_default_mreg_copy_pattern_template).

Fixes: 593fb3fdfa10 ("net/mlx5: fix multi process Tx default rules")

Signed-off-by: Shani Peretz <shperetz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 42 +--------------------------------
 1 file changed, 1 insertion(+), 41 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 208f50fbfd..b64ba9b46b 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -10185,46 +10185,6 @@ flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
 	return flow_hw_pattern_template_create(dev, &attr, items, error);
 }
 
-/*
- * Creating a flow pattern template with all ETH packets matching.
- * This template is used to set up a table for default Tx copy (Tx metadata
- * to REG_C_1) flow rule usage.
- *
- * @param dev
- *   Pointer to Ethernet device.
- * @param error
- *   Pointer to error structure.
- *
- * @return
- *   Pointer to flow pattern template on success, NULL otherwise.
- */
-static struct rte_flow_pattern_template *
-flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
-						     struct rte_flow_error *error)
-{
-	struct rte_flow_pattern_template_attr tx_pa_attr = {
-		.relaxed_matching = 0,
-		.egress = 1,
-	};
-	struct rte_flow_item_eth promisc = {
-		.hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
-		.hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
-		.hdr.ether_type = 0,
-	};
-	struct rte_flow_item eth_all[] = {
-		[0] = {
-			.type = RTE_FLOW_ITEM_TYPE_ETH,
-			.spec = &promisc,
-			.mask = &promisc,
-		},
-		[1] = {
-			.type = RTE_FLOW_ITEM_TYPE_END,
-		},
-	};
-
-	return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
-}
-
 /*
  * Creating a flow pattern template with all LACP packets matching, only for NIC
  * ingress domain.
@@ -10930,7 +10890,7 @@ flow_hw_create_fdb_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *e
 	/* Create templates and table for default Tx metadata copy flow rule. */
 	if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
 		hw_ctrl_fdb->tx_meta_items_tmpl =
-			flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
+			flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
 		if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
 			DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
 				" template for control flows", dev->data->port_id);
-- 
2.34.1

Re: [PATCH 22.11] net/mlx5: fix Tx metadata pattern template mismatch

[Luca Boccassi]

On Thu, 20 Nov 2025 at 10:48, Shani Peretz <shperetz@nvidia.com> wrote:
>
> When representor matching is disabled with dv_xmeta_en=4, the Tx metadata
> copy flows use SQ (send queue) pattern matching, but the pattern template
> was still configured to use ETH match-all pattern. This mismatch causes
> hardware to reject the flows with error CQEs during port configuration.
>
> This patch fixes the issue by using SQ-based pattern template
> (flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all
> template (flow_hw_create_tx_default_mreg_copy_pattern_template).
>
> Fixes: 593fb3fdfa10 ("net/mlx5: fix multi process Tx default rules")
>
> Signed-off-by: Shani Peretz <shperetz@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> ---
>  drivers/net/mlx5/mlx5_flow_hw.c | 42 +--------------------------------
>  1 file changed, 1 insertion(+), 41 deletions(-)

Hi, thanks for the patch, unfortunately this does not apply, neither
on https://git.dpdk.org/dpdk-stable/log/?h=22.11 nor on
https://github.com/bluca/dpdk-stable/tree/22.11

How was this tested?

RE: [PATCH 22.11] net/mlx5: fix Tx metadata pattern template mismatch

[Shani Peretz]

> -----Original Message-----
> From: Luca Boccassi <luca.boccassi@gmail.com>
> Sent: Thursday, 20 November 2025 14:41
> To: Shani Peretz <shperetz@nvidia.com>
> Cc: stable@dpdk.org; Dariusz Sosnowski <dsosnowski@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Ori Kam
> <orika@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; Michael Baum <michaelba@nvidia.com>; NBU-Contact-
> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>
> Subject: Re: [PATCH 22.11] net/mlx5: fix Tx metadata pattern template
> mismatch
> 
> External email: Use caution opening links or attachments
> 
> 
> On Thu, 20 Nov 2025 at 10:48, Shani Peretz <shperetz@nvidia.com> wrote:
> >
> > When representor matching is disabled with dv_xmeta_en=4, the Tx
> > metadata copy flows use SQ (send queue) pattern matching, but the
> > pattern template was still configured to use ETH match-all pattern.
> > This mismatch causes hardware to reject the flows with error CQEs during
> port configuration.
> >
> > This patch fixes the issue by using SQ-based pattern template
> > (flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all
> > template (flow_hw_create_tx_default_mreg_copy_pattern_template).
> >
> > Fixes: 593fb3fdfa10 ("net/mlx5: fix multi process Tx default rules")
> >
> > Signed-off-by: Shani Peretz <shperetz@nvidia.com>
> > Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> > ---
> >  drivers/net/mlx5/mlx5_flow_hw.c | 42
> > +--------------------------------
> >  1 file changed, 1 insertion(+), 41 deletions(-)
> 
> Hi, thanks for the patch, unfortunately this does not apply, neither on
> https://git.dpdk.org/dpdk-stable/log/?h=22.11 nor on
> https://github.com/bluca/dpdk-stable/tree/22.11
> 
> How was this tested?


Hi Luca,
I'm sorry for this, I tested it on upstream so maybe they diverged.
anyway I sent v2. tested on top of https://github.com/bluca/dpdk-stable/tree/22.11

[PATCH 22.11 v2] net/mlx5: fix Tx metadata pattern template mismatch

[Shani Peretz]

When representor matching is disabled with dv_xmeta_en=4, the Tx metadata
copy flows use SQ (send queue) pattern matching, but the pattern template
was still configured to use ETH match-all pattern. This mismatch causes
hardware to reject the flows with error CQEs during port configuration.

This patch fixes the issue by using SQ-based pattern template
(flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all
template (flow_hw_create_tx_default_mreg_copy_pattern_template).

Fixes: 4f0537afcc45 ("net/mlx5: fix multi-process Tx default rules")

Signed-off-by: Shani Peretz <shperetz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 42 +--------------------------------
 1 file changed, 1 insertion(+), 41 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index a85b49d284..1ca8c8cd80 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5781,46 +5781,6 @@ flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
 	return flow_hw_pattern_template_create(dev, &attr, items, error);
 }
 
-/*
- * Creating a flow pattern template with all ETH packets matching.
- * This template is used to set up a table for default Tx copy (Tx metadata
- * to REG_C_1) flow rule usage.
- *
- * @param dev
- *   Pointer to Ethernet device.
- * @param error
- *   Pointer to error structure.
- *
- * @return
- *   Pointer to flow pattern template on success, NULL otherwise.
- */
-static struct rte_flow_pattern_template *
-flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
-						     struct rte_flow_error *error)
-{
-	struct rte_flow_pattern_template_attr tx_pa_attr = {
-		.relaxed_matching = 0,
-		.egress = 1,
-	};
-	struct rte_flow_item_eth promisc = {
-		.dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
-		.src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
-		.type = 0,
-	};
-	struct rte_flow_item eth_all[] = {
-		[0] = {
-			.type = RTE_FLOW_ITEM_TYPE_ETH,
-			.spec = &promisc,
-			.mask = &promisc,
-		},
-		[1] = {
-			.type = RTE_FLOW_ITEM_TYPE_END,
-		},
-	};
-
-	return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
-}
-
 /*
  * Creating a flow pattern template with all LACP packets matching, only for NIC
  * ingress domain.
@@ -6523,7 +6483,7 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error
 	/* Create templates and table for default Tx metadata copy flow rule. */
 	if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
 		hw_ctrl_fdb->tx_meta_items_tmpl =
-			flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
+			flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
 		if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
 			DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
 				" template for control flows", dev->data->port_id);
-- 
2.34.1