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Wed, 8 Mar 2023 17:58:25 -0800 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (104.47.57.46) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.21; Wed, 8 Mar 2023 17:58:25 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Unu69GBOaF/0lmkQPUCQJghPW/2qP4FB4QapYqY227yCC1H/tNNaQlmlGTJDGK6qqEtx6udw2ofjCesLXeij7OD4L+kb8M+lIvz6tuqdUBn+MaRvz7pMDXLI5ZhSBEg1JQUCaKr9DdR37mwXhmeUFXtgH1bYJNR8LiYLTtq7Zb5w4r7qrlS2jGgW9b/2pmZWU8/GNroObKBiLpAUUNu27M+otk1hsahpW/cXqWdFoE7J9vLreRqclyBg9su4YhL6+Q1uu/qFp7O+WHwSwY/QvjjbEDFE2lZ4HT9aFeQBNFofCj1z00E6N7rvUlxSP4WavFasbaEZ7ImKsJ60mTJdpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3ahSqdkj5J2NDFPbRS9PFGo9i0gybiFxsWfke/njHK0=; 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ0PR11MB6765.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0465860b-d873-4936-13b5-08db2041c332 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Mar 2023 01:58:22.2547 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fZ8DVRNVBn3t/FsdzwmH8yD6PW7nNxNFOevVYrtuVp3Yem9Ye+Gn3BMjG6jTkWE21idyWS4Nq3HJGNUhyCIWXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR11MB6611 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Thomas Monjalon > Sent: 2023=1B$BG/=1B(B3=1B$B7n=1B(B3=1B$BF|=1B(B 22:07 > To: Burakov, Anatoly ; You, KaisenX > > Cc: dev@dpdk.org; Zhou, YidingX ; > david.marchand@redhat.com; Matz, Olivier ; > ferruh.yigit@amd.com; zhoumin@loongson.cn; stable@dpdk.org; > Richardson, Bruce ; jerinj@marvell.com > Subject: Re: [PATCH v5] enhance NUMA affinity heuristic >=20 > I'm not comfortable with this patch. >=20 > First, there is no comment in the code which helps to understand the logi= c. > Second, I'm afraid changing the value of the per-core variable _socket_id > may have an impact on some applications. >=20 Thank you for your reply. First, about comments, I can submit a new patch to add comments to help und= erstand. Second, if you do not change the value of the per-core variable_ socket_ id= , /lib/eal/common/malloc_heap.c malloc_get_numa_socket(void) { const struct internal_config *conf =3D eal_get_internal_configurati= on(); unsigned int socket_id =3D rte_socket_id(); // The return value o= f "rte_socket_id()" is 1 unsigned int idx; if (socket_id !=3D (unsigned int)SOCKET_ID_ANY) return socket_id; //so return here=20 This will cause return here, This function returns the socket_id of unalloc= ated memory. If you have a better solution, I can modify it. > 16/02/2023 03:50, You, KaisenX: > > From: Burakov, Anatoly > > > On 2/1/2023 12:20 PM, Kaisen You wrote: > > > > Trying to allocate memory on the first detected numa node has less > > > > chance to find some memory actually available rather than on the > > > > main lcore numa node (especially when the DPDK application is > > > > started only on one numa node). > > > > > > > > Fixes: 705356f0811f ("eal: simplify control thread creation") > > > > Fixes: bb0bd346d5c1 ("eal: suggest using --lcores option") > > > > Cc: stable@dpdk.org > > > > > > > > Signed-off-by: David Marchand > > > > Signed-off-by: Kaisen You > > > > --- > > > > Changes since v4: > > > > - mod the patch title, > > > > > > > > Changes since v3: > > > > - add the assignment of socket_id in thread initialization, > > > > > > > > Changes since v2: > > > > - add uncommitted local change and fix compilation, > > > > > > > > Changes since v1: > > > > - accomodate for configurations with main lcore running on multiple= s > > > > physical cores belonging to different numa, > > > > --- > > > > lib/eal/common/eal_common_thread.c | 1 + > > > > lib/eal/common/malloc_heap.c | 4 ++++ > > > > 2 files changed, 5 insertions(+) > > > > > > > > diff --git a/lib/eal/common/eal_common_thread.c > > > > b/lib/eal/common/eal_common_thread.c > > > > index 38d83a6885..21bff971f8 100644 > > > > --- a/lib/eal/common/eal_common_thread.c > > > > +++ b/lib/eal/common/eal_common_thread.c > > > > @@ -251,6 +251,7 @@ static void *ctrl_thread_init(void *arg) > > > > void *routine_arg =3D params->arg; > > > > > > > > __rte_thread_init(rte_lcore_id(), cpuset); > > > > + RTE_PER_LCORE(_socket_id) =3D SOCKET_ID_ANY; > > > > params->ret =3D rte_thread_set_affinity_by_id(rte_thread_self(), > > > cpuset); > > > > if (params->ret !=3D 0) { > > > > __atomic_store_n(¶ms->ctrl_thread_status, > > > > diff --git a/lib/eal/common/malloc_heap.c > > > > b/lib/eal/common/malloc_heap.c index d7c410b786..3ee19aee15 > 100644 > > > > --- a/lib/eal/common/malloc_heap.c > > > > +++ b/lib/eal/common/malloc_heap.c > > > > @@ -717,6 +717,10 @@ malloc_get_numa_socket(void) > > > > return socket_id; > > > > } > > > > > > > > + socket_id =3D rte_lcore_to_socket_id(rte_get_main_lcore()); > > > > + if (socket_id !=3D (unsigned int)SOCKET_ID_ANY) > > > > + return socket_id; > > > > + > > > > return rte_socket_id_by_idx(0); > > > > } > > > > > > > > > > I may be lacking context, but I don't quite get the suggested change. > > > From what I understand, the original has to do with assigning lcore > > > cpusets in such a way that an lcore ends up having two socket ID's > > > (because it's been assigned to CPU's on different sockets). Why is th= is > allowed in the first place? > > > It seems like a user error to me, as it breaks many of the > > > fundamental assumptions DPDK makes. > > > > > In a dual socket system, if all used cores are in socket 1 and the NIC > > is in socket 1, no memory is allocated for socket 0. This is to optimiz= e > memory consumption. > > > > I agree with you. If the startup parameters can ensure that both > > sockets allocate memory, there will be no problem. > > However, due to the different CPU topologies of different systems, It > > is difficult for users to ensure that the startup parameter contains tw= o cpu > nodes. > > > > > I'm fine with using main lcore socket for control threads, I just > > > don't think the `socket_id !=3D SOCKET_ID_ANY` thing should be checke= d > > > here, because it apparently tries to compensate for a problem with > > > cpuset of the main thread, which shouldn't have happened to begin wit= h. > > > > > This issue has been explained in detail in the discussion of the patch = v1 > version. > > I will forward the previous email to you. The content of the email > > will also better let you know the purpose of submitting this patch. >=20 >=20