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Wed, 8 Aug 2018 01:39:37 +0000 From: Gavin Hu To: Thomas Monjalon CC: "dev@dpdk.org" , Honnappa Nagarahalli , Steve Capper , Ola Liljedahl , "jerin.jacob@caviumnetworks.com" , "hemant.agrawal@nxp.com" , "jia.he@hxt-semitech.com" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] ring: fix c11 memory ordering issue Thread-Index: AQHULSNjpUJVIWULMUiw1lQiKNltiKSyctYAgAKhCJA= Date: Wed, 8 Aug 2018 01:39:37 +0000 Message-ID: References: <20180806011805.7857-1-gavin.hu@arm.com> <1937068.bZVvs4nVfc@xps> In-Reply-To: <1937068.bZVvs4nVfc@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VI1PR08MB3678; 6:/5jjB8QeLRgmvJuQVbRj6AKRxhvP/CCMmSwgwp6AG0OYS7orDyxhCC5afiVYj3rUtdFmq6W6w6Ov3oLTft1pUolJ0iW49kHtXJW7eDodBUnN78a8R49PyDO5EqWYxqAbru86MItQIH1cmDIjO6GyzBhLjgOBWt5I7Ox7eXwCrfmRRiFzih22mg6NSYLWvfB42Ln2EugdyKBXROZ4EsKRcnSrb4LlhoK6NZzSDpvc6Prt2c8QoHF8SzhnLb8AubKiXqE5P9PXLORw9SAveWsAJDRFNUWiUBqj1rkhUt6zSooJRDuldlx/g6LyMx90nIZyMp0nmpiZqIKqENqt1H53s4/a7QYI1IfsvUzLBXyw3mB6LfaCU/NLRTsZIFGAe6Yd3ppWanG7ltywz34HDlXUJhq/hgGVb0HPgUMgXNLsQt+9TxSdgR8KVgBhSG4sSm0SQ/tinBR/mjX4VIHjfKynnw==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR08MB3678; H:VI1PR08MB3167.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: UnPj7IdckUYaqKi4zUJnPwRaZ4s6/7YwsVEBp0d16bXeUDTVAPvt11h41vwmGxfihjXGhVR0/B+xRwP5Z9KJDfBVqPDs8HMCUwyyxjUGDckZdGQmYob90bJ8ApFdSaMyK+mld5VFftXx5ZNe8/dQ5y+/LQ/RbTXyS5yoFzpdZCak/IgMV6aD3qKyxuQWVhst0vJac69+GdQa7dN8OQC1a7aoitgKHx2AQ3jKkcEHiNqrm3fujHathEztVh/SvhPeTYqyuS68PWPOhmcnrNT2TcxXkCixdgaoK8xXOkDW2Ygd+hBRuQ9tlO4p0ewcbCl6iV0rYD9xOYAfHfs31KRXpriX5iCxRdVeUT2fOYQOuX8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: af783662-fedb-49a1-722c-08d5fccfcd59 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Aug 2018 01:39:37.4642 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3678 Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH] ring: fix c11 memory ordering issue X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Aug 2018 01:39:40 -0000 Hi Thomas, I updated the commit message in my v2 patch. Could you check if your questions get answered by the new commit message an= d this mail? And what's your opinions of splitting the patch into 4 smaller ones(2 bug f= ixes and 2 optimizations)? I got this comment from Jia He, he is the author= of this file. >>What is the consequence of the bug on the behaviour? Potential effects could be read of stale values. >> What is the scope of the bug? only PPC? The scope is all weakly ordered architectures such as ARM (32- and 64-bit) = and POWER. -----Original Message----- From: Thomas Monjalon Sent: 2018=1B$BG/=1B(B8=1B$B7n=1B(B6=1B$BF|=1B(B 17:19 To: Gavin Hu Cc: dev@dpdk.org; Honnappa Nagarahalli ; Stev= e Capper ; Ola Liljedahl ; jer= in.jacob@caviumnetworks.com; hemant.agrawal@nxp.com; jia.he@hxt-semitech.co= m; stable@dpdk.org Subject: Re: [dpdk-dev] [PATCH] ring: fix c11 memory ordering issue Hi, Please start your patch by explaining the issue you are solving. What is the consequence of the bug on the behaviour? What is the scope of the bug? only PPC? 06/08/2018 03:18, Gavin Hu: > 1) In update_tail, read ht->tail using __atomic_load. > 2) In __rte_ring_move_prod_head, move the __atomic_load_n up and out of > the do {} while loop as upon failure the old_head will be updated, > another load is not necessary. > 3) Synchronize the load-acquires of prod.tail and cons.tail with store- > releases of update_tail which releases all ring updates up to the > value of ht->tail. > 4) When calling __atomic_compare_exchange_n, relaxed ordering for both > success and failure, as multiple threads can work independently on > the same end of the ring (either enqueue or dequeue) without > synchronization, not as operating on tail, which has to be finished > in sequence. > > Fixes: 39368ebfc6 ("ring: introduce C11 memory model barrier option") > Cc: stable@dpdk.org > > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Steve Capper > Reviewed-by: Ola Liljedahl > Signed-off-by: Gavin Hu Your Signed-off-by should be first in the list. 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