From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81C49A0C41 for ; Fri, 8 Oct 2021 12:16:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73900410DC; Fri, 8 Oct 2021 12:16:23 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id AA23C40DF7; Fri, 8 Oct 2021 12:16:20 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="223887161" X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="223887161" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 03:15:35 -0700 X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="478927845" Received: from bricha3-mobl.ger.corp.intel.com ([10.252.21.2]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 08 Oct 2021 03:15:33 -0700 Date: Fri, 8 Oct 2021 11:15:28 +0100 From: Bruce Richardson To: David Marchand Cc: dev@dpdk.org, stable@dpdk.org, Konstantin Ananyev Message-ID: References: <20211006192008.23369-1-david.marchand@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211006192008.23369-1-david.marchand@redhat.com> Subject: Re: [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On Wed, Oct 06, 2021 at 09:20:08PM +0200, David Marchand wrote: > Caught while checking CPUID related stuff in OVS. > > According to [1], for Structured Extended Feature Flags Enumeration Leaf > (EAX = 0x07H, ECX = 0): > > - BMI1 is associated to EBX, bit 3 (was incorrectly 2), > - SMEP is associated to EBX, bit 7 (was incorrectly 6), > - BMI2 is associated to EBX, bit 8 (was incorrectly 7), > - ERMS is associated to EBX, bit 9 (was incorrectly 8), > > This patch then sorts the rest of the extended features (leaf 0) for > readability. > > 1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Fixes: af75078fece3 ("first public release") Wow, I'm surprised at it being incorrect this long, but checking the original commit of code, it does indeed seem true that this is the correct fixes line! > Cc: stable@dpdk.org > > Signed-off-by: David Marchand Acked-by: Bruce Richardson Ideally, I think the fixes should go in a separate patch from the reordering, but I don't feel strongly about it so this is ok as either one or two patches IMHO. > --- > lib/eal/x86/rte_cpuflags.c | 46 +++++++++++++++++++------------------- > 1 file changed, 23 insertions(+), 23 deletions(-) > > diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c > index d339734a8c..d6b518251b 100644 > --- a/lib/eal/x86/rte_cpuflags.c > +++ b/lib/eal/x86/rte_cpuflags.c > @@ -100,18 +100,36 @@ const struct feature_entry rte_cpu_feature_table[] = { > FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) > > FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) > - FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) > + FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 3) > FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) > FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) > - FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) > - FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) > - FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) > + FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 7) > + FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 8) > + FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 9) > FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) > FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) > FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) > + FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17) > FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18) > + FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21) > + FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28) > + FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30) > + FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31) > + > + FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1) > + FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5) > + FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6) > + FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8) > + FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9) > + FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10) > + FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11) > + FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12) > + FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14) > + FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25) > + FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27) > + FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28) > > - FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5) > + FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8) > > FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) > FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) > @@ -123,24 +141,6 @@ const struct feature_entry rte_cpu_feature_table[] = { > FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) > > FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) > - > - FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17) > - FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21) > - FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28) > - FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30) > - FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31) > - FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1) > - FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6) > - FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8) > - FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9) > - FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10) > - FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11) > - FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12) > - FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14) > - FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25) > - FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27) > - FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28) > - FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8) > }; > > int > -- > 2.23.0 >