Re: [PATCH 15/16] net/dpaa: fix bitmask truncation

[Hemant Agrawal <hemant.agrawal@oss.nxp.com>]

Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

On 15-11-2024 11:35, Stephen Hemminger wrote:
> The dqrr_held mask is 64 bit but updates were getting truncated
> because 1 is of type int (32 bit) and the result shift of int is of
> type int (32 bit); therefore any value >= 32 would get truncated.
>
> Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
>
> Fixes: 5e7455931442 ("net/dpaa: support Rx queue configurations with eventdev")
> Cc: sunil.kori@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/net/dpaa/dpaa_rxtx.c | 7 +++----
>   1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
> index 247e7b92ba..05bd73becf 100644
> --- a/drivers/net/dpaa/dpaa_rxtx.c
> +++ b/drivers/net/dpaa/dpaa_rxtx.c
> @@ -842,7 +842,7 @@ dpaa_rx_cb_atomic(void *event,
>   	/* Save active dqrr entries */
>   	index = DQRR_PTR2IDX(dqrr);
>   	DPAA_PER_LCORE_DQRR_SIZE++;
> -	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
> +	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
>   	DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf;
>   	ev->impl_opaque = index + 1;
>   	*dpaa_seqn(mbuf) = (uint32_t)index + 1;
> @@ -1338,13 +1338,12 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
>   			seqn = *dpaa_seqn(mbuf);
>   			if (seqn != DPAA_INVALID_MBUF_SEQN) {
>   				index = seqn - 1;
> -				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
> +				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
>   					flags[loop] =
>   					   ((index & QM_EQCR_DCA_IDXMASK) << 8);
>   					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
>   					DPAA_PER_LCORE_DQRR_SIZE--;
> -					DPAA_PER_LCORE_DQRR_HELD &=
> -								~(1 << index);
> +					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
>   				}
>   			}
>