From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5085A0C49 for ; Wed, 16 Jun 2021 20:43:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE1064067A; Wed, 16 Jun 2021 20:43:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 10F044067A for ; Wed, 16 Jun 2021 20:43:01 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15GIVV4o023431; Wed, 16 Jun 2021 11:43:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=E2Wy/h3KgoEABzGjOW/j+J26pBqduPn5cDvcvuQrL7Y=; b=OpIFK2Wcc8Tjj6XFXXLVPvU6HRXS9vVHXd9CkeoCoUxC2KvhaGgMFN8PjW1SRT6mPOSV ESjrsdsKDgyw2aSl1FxYw0njh2rcJ7pvfzIuSpCcYkx5t25kC6mQyVi6k7iRFUG8lMj1 mXF8lMZEAPRCoRrt/QpJQn/zKRebblFkudmnHGXo0gLBljWhIZRD5UpGram+9/X7c+gC hevSYqDTDNvf9ouEJHPsHG4Z4s3n8DSgA+k7TADOVfCMlZChCiwCMNrZ5uwnzrNfODbH uiHjUeP1d0+0N37/exU1oLOVXtEUDaEpOGhxRewPxAwTvO9MeG+GvUlJ4G9NyZQ29ZG3 iA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 396tagyy0d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 16 Jun 2021 11:43:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 16 Jun 2021 11:42:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 16 Jun 2021 11:42:57 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id E30723F7071; Wed, 16 Jun 2021 11:42:55 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , , , Ankur Dwivedi Date: Thu, 17 Jun 2021 00:12:08 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 6szxc17e73s_Ex1ZLAO5JK00sSDoXn5X X-Proofpoint-GUID: 6szxc17e73s_Ex1ZLAO5JK00sSDoXn5X X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-16_11:2021-06-15, 2021-06-16 signatures=0 Subject: [dpdk-stable] [PATCH 20.11 1/3] event/octeontx2: fix crypto adapter queue pair operations X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" [ upstream commit 3841fc3581ec4d95bf8a72e8a545db8d03ecd2bd ] Parameter queue_pair_id of crypto adapter queue pair add/del operation can be -1 to select all pre configured crypto queue pairs. Added support for the same in driver. Also added a member in cpt qp structure to indicate binding state of a queue pair to an event queue. Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework") Signed-off-by: Shijith Thotton Acked-by: Ankur Dwivedi --- drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 4 +- .../event/octeontx2/otx2_evdev_crypto_adptr.c | 102 ++++++++++++------ 2 files changed, 75 insertions(+), 31 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h index 96ff4eb41..499d54e3e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) 2020 Marvell International Ltd. + * Copyright (C) 2020-2021 Marvell. */ #ifndef _OTX2_CRYPTODEV_QP_H_ @@ -37,6 +37,8 @@ struct otx2_cpt_qp { */ uint8_t ca_enable; /**< Set when queue pair is added to crypto adapter */ + uint8_t qp_ev_bind; + /**< Set when queue pair is bound to event queue */ }; #endif /* _OTX2_CRYPTODEV_QP_H_ */ diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index 7197815ae..c6a4fbaf4 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) 2020 Marvell International Ltd. + * Copyright (C) 2020-2021 Marvell. */ #include #include +#include "otx2_cryptodev.h" #include "otx2_cryptodev_hw_access.h" #include "otx2_cryptodev_qp.h" #include "otx2_cryptodev_mbox.h" @@ -23,30 +24,66 @@ otx2_ca_caps_get(const struct rte_eventdev *dev, return 0; } -int -otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, - int32_t queue_pair_id, const struct rte_event *event) +static int +otx2_ca_qp_sso_link(const struct rte_cryptodev *cdev, struct otx2_cpt_qp *qp, + uint16_t sso_pf_func) { - struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev); union otx2_cpt_af_lf_ctl2 af_lf_ctl2; - struct otx2_cpt_qp *qp; int ret; - qp = cdev->data->queue_pairs[queue_pair_id]; - - qp->ca_enable = 1; - rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); - ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - &af_lf_ctl2.u); + &af_lf_ctl2.u); if (ret) return ret; - af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get(); + af_lf_ctl2.s.sso_pf_func = sso_pf_func; ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - af_lf_ctl2.u); - if (ret) - return ret; + af_lf_ctl2.u); + return ret; +} + +static void +otx2_ca_qp_init(struct otx2_cpt_qp *qp, const struct rte_event *event) +{ + if (event) { + qp->qp_ev_bind = 1; + rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); + } else { + qp->qp_ev_bind = 0; + } + qp->ca_enable = 1; +} + +int +otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id, const struct rte_event *event) +{ + struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev); + struct otx2_cpt_vf *vf = cdev->data->dev_private; + uint16_t sso_pf_func = otx2_sso_pf_func_get(); + struct otx2_cpt_qp *qp; + uint8_t qp_id; + int ret; + + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func); + if (ret) { + uint8_t qp_tmp; + for (qp_tmp = 0; qp_tmp < qp_id; qp_tmp++) + otx2_ca_qp_del(dev, cdev, qp_tmp); + return ret; + } + otx2_ca_qp_init(qp, event); + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func); + if (ret) + return ret; + otx2_ca_qp_init(qp, event); + } sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); @@ -58,24 +95,29 @@ int otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, int32_t queue_pair_id) { - union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_vf *vf = cdev->data->dev_private; struct otx2_cpt_qp *qp; + uint8_t qp_id; int ret; RTE_SET_USED(dev); - qp = cdev->data->queue_pairs[queue_pair_id]; - qp->ca_enable = 0; - memset(&qp->ev, 0, sizeof(struct rte_event)); + ret = 0; + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, 0); + if (ret) + return ret; + qp->ca_enable = 0; + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, 0); + if (ret) + return ret; + qp->ca_enable = 0; + } - ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - &af_lf_ctl2.u); - if (ret) - return ret; - - af_lf_ctl2.s.sso_pf_func = 0; - ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - af_lf_ctl2.u); - - return ret; + return 0; } -- 2.25.1