From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id 0E5381B10C for ; Mon, 26 Nov 2018 16:42:07 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 33828811D9; Mon, 26 Nov 2018 15:42:06 +0000 (UTC) Received: from ktraynor.remote.csb (ovpn-117-230.ams2.redhat.com [10.36.117.230]) by smtp.corp.redhat.com (Postfix) with ESMTP id 51F635C88B; Mon, 26 Nov 2018 15:42:04 +0000 (UTC) To: Tiwei Bie Cc: Brian Russell , Luca Boccassi , dpdk stable References: <20181123102713.17309-1-ktraynor@redhat.com> <20181123102713.17309-6-ktraynor@redhat.com> <20181126020231.GA16607@debian> From: Kevin Traynor Organization: Red Hat Message-ID: Date: Mon, 26 Nov 2018 15:42:03 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: <20181126020231.GA16607@debian> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 26 Nov 2018 15:42:06 +0000 (UTC) Subject: Re: [dpdk-stable] patch 'net/virtio: fix PCI config error handling' has been queued to stable release 18.08.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 15:42:07 -0000 On 11/26/2018 02:02 AM, Tiwei Bie wrote: > On Fri, Nov 23, 2018 at 10:26:10AM +0000, Kevin Traynor wrote: >> Hi, >> >> FYI, your patch has been queued to stable release 18.08.1 >> >> Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. >> It will be pushed if I get no objections before 11/29/18. So please >> shout if anyone has objections. > > Hi, > > This patch can't be backported, as it depends on some API > change in newer release. > Thanks Tiwei, I will drop from backports. > Thanks, > Tiwei > >> >> Also note that after the patch there's a diff of the upstream commit vs the patch applied >> to the branch. If the code is different (ie: not only metadata diffs), due for example to >> a change in context or macro names, please double check it. >> >> Thanks. >> >> Kevin Traynor >> >> --- >> From e0af7542c97f172f44d633389d33920b889e8b22 Mon Sep 17 00:00:00 2001 >> From: Brian Russell >> Date: Tue, 28 Aug 2018 11:12:40 +0100 >> Subject: [PATCH] net/virtio: fix PCI config error handling >> >> [ upstream commit 49bb1f7a0ab760a0f1fb39e27c90a1cb2ad42edd ] >> >> In virtio_read_caps and vtpci_msix_detect, rte_pci_read_config returns >> the number of bytes read from PCI config or < 0 on error. >> If less than the expected number of bytes are read then log the >> failure and return rather than carrying on with garbage. >> >> Fixes: 6ba1f63b5ab0 ("virtio: support specification 1.0") >> >> Signed-off-by: Brian Russell >> Signed-off-by: Luca Boccassi >> Reviewed-by: Tiwei Bie >> --- >> drivers/net/virtio/virtio_pci.c | 65 ++++++++++++++++++++++++--------- >> 1 file changed, 48 insertions(+), 17 deletions(-) >> >> diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c >> index 6bd22e54a..b6a3c80b4 100644 >> --- a/drivers/net/virtio/virtio_pci.c >> +++ b/drivers/net/virtio/virtio_pci.c >> @@ -568,14 +568,16 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) >> >> ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST); >> - if (ret < 0) { >> - PMD_INIT_LOG(DEBUG, "failed to read pci capability list"); >> + if (ret != 1) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci capability list, ret %d", ret); >> return -1; >> } >> >> while (pos) { >> - ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos); >> - if (ret < 0) { >> - PMD_INIT_LOG(ERR, >> - "failed to read pci cap at pos: %x", pos); >> + ret = rte_pci_read_config(dev, &cap, 2, pos); >> + if (ret != 2) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci cap at pos: %x ret %d", >> + pos, ret); >> break; >> } >> @@ -587,5 +589,14 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) >> * cap; next two bytes are the flags. >> */ >> - uint16_t flags = ((uint16_t *)&cap)[1]; >> + uint16_t flags; >> + >> + ret = rte_pci_read_config(dev, &flags, sizeof(flags), >> + pos + 2); >> + if (ret != sizeof(flags)) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci cap at pos:" >> + " %x ret %d", pos + 2, ret); >> + break; >> + } >> >> if (flags & PCI_MSIX_ENABLE) >> @@ -602,4 +613,12 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) >> } >> >> + ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos); >> + if (ret != sizeof(cap)) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci cap at pos: %x ret %d", >> + pos, ret); >> + break; >> + } >> + >> PMD_INIT_LOG(DEBUG, >> "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u", >> @@ -690,23 +709,35 @@ vtpci_msix_detect(struct rte_pci_device *dev) >> { >> uint8_t pos; >> - struct virtio_pci_cap cap; >> int ret; >> >> ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST); >> - if (ret < 0) { >> - PMD_INIT_LOG(DEBUG, "failed to read pci capability list"); >> + if (ret != 1) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci capability list, ret %d", ret); >> return VIRTIO_MSIX_NONE; >> } >> >> while (pos) { >> - ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos); >> - if (ret < 0) { >> - PMD_INIT_LOG(ERR, >> - "failed to read pci cap at pos: %x", pos); >> + uint8_t cap[2]; >> + >> + ret = rte_pci_read_config(dev, cap, sizeof(cap), pos); >> + if (ret != sizeof(cap)) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci cap at pos: %x ret %d", >> + pos, ret); >> break; >> } >> >> - if (cap.cap_vndr == PCI_CAP_ID_MSIX) { >> - uint16_t flags = ((uint16_t *)&cap)[1]; >> + if (cap[0] == PCI_CAP_ID_MSIX) { >> + uint16_t flags; >> + >> + ret = rte_pci_read_config(dev, &flags, sizeof(flags), >> + pos + sizeof(cap)); >> + if (ret != sizeof(flags)) { >> + PMD_INIT_LOG(DEBUG, >> + "failed to read pci cap at pos:" >> + " %x ret %d", pos + 2, ret); >> + break; >> + } >> >> if (flags & PCI_MSIX_ENABLE) >> @@ -716,5 +747,5 @@ vtpci_msix_detect(struct rte_pci_device *dev) >> } >> >> - pos = cap.cap_next; >> + pos = cap[1]; >> } >> >> -- >> 2.19.0 >> >> --- >> Diff of the applied patch vs upstream commit (please double-check if non-empty: >> --- >> --- - 2018-11-23 10:22:54.406494254 +0000 >> +++ 0006-net-virtio-fix-PCI-config-error-handling.patch 2018-11-23 10:22:54.000000000 +0000 >> @@ -1,15 +1,16 @@ >> -From 49bb1f7a0ab760a0f1fb39e27c90a1cb2ad42edd Mon Sep 17 00:00:00 2001 >> +From e0af7542c97f172f44d633389d33920b889e8b22 Mon Sep 17 00:00:00 2001 >> From: Brian Russell >> Date: Tue, 28 Aug 2018 11:12:40 +0100 >> Subject: [PATCH] net/virtio: fix PCI config error handling >> >> +[ upstream commit 49bb1f7a0ab760a0f1fb39e27c90a1cb2ad42edd ] >> + >> In virtio_read_caps and vtpci_msix_detect, rte_pci_read_config returns >> the number of bytes read from PCI config or < 0 on error. >> If less than the expected number of bytes are read then log the >> failure and return rather than carrying on with garbage. >> >> Fixes: 6ba1f63b5ab0 ("virtio: support specification 1.0") >> -Cc: stable@dpdk.org >> >> Signed-off-by: Brian Russell >> Signed-off-by: Luca Boccassi