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Date: Thu, 24 Nov 2016 02:32:55 +0100 (CET)
From: checkpatch@dpdk.org
Subject: [dpdk-test-report] |WARNING| [PATCH 02/16] e1000/base: increase PHY
	PLL clock gate timing
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Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/17210

_coding style issues_


WARNING:TABSTOP: Statements should start on a tabstop
#73: FILE: drivers/net/e1000/base/e1000_ich8lan.c:1503:
+		 }

total: 0 errors, 1 warnings, 0 checks, 30 lines checked