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Subject: |WARNING| pw112452 [PATCH RESEND v4 1/8] eal: add initial support for
 RISC-V architecture
In-Reply-To: <20220607104617.153892-2-kda@semihalf.com>
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To: test-report@dpdk.org
From: checkpatch@dpdk.org
Cc: Stanislaw Kardach <kda@semihalf.com>
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Date: Tue,  7 Jun 2022 12:47:41 +0200 (CEST)
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Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/112452

_coding style issues_


WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
#137: 
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>

WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
#138: 
Sponsored-by: Sam Grove <sam.grove@sifive.com>

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#815: FILE: lib/eal/riscv/include/rte_atomic.h:24:
+#define rte_mb()	asm volatile("fence rw, rw" : : : "memory")

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#817: FILE: lib/eal/riscv/include/rte_atomic.h:26:
+#define rte_wmb()	asm volatile("fence w, w" : : : "memory")

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#819: FILE: lib/eal/riscv/include/rte_atomic.h:28:
+#define rte_rmb()	asm volatile("fence r, r" : : : "memory")

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#827: FILE: lib/eal/riscv/include/rte_atomic.h:36:
+#define rte_io_mb()	asm volatile("fence iorw, iorw" : : : "memory")

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#829: FILE: lib/eal/riscv/include/rte_atomic.h:38:
+#define rte_io_wmb()	asm volatile("fence orw, ow" : : : "memory")

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#831: FILE: lib/eal/riscv/include/rte_atomic.h:40:
+#define rte_io_rmb()	asm volatile("fence ir, ir" : : : "memory")

WARNING:TYPO_SPELLING: 'hart' may be misspelled - perhaps 'heart'?
#998: FILE: lib/eal/riscv/include/rte_cycles.h:38:
+/** Read hart cycle counter */

WARNING:TYPO_SPELLING: 'hart' may be misspelled - perhaps 'heart'?
#1007: FILE: lib/eal/riscv/include/rte_cycles.h:47:
+/** Read hart cycle counter ensuring no re-ordering */

total: 6 errors, 4 warnings, 1424 lines checked
Warning in lib/eal/riscv/include/rte_vect.h:
Using compiler attribute directly
Warning in lib/eal/riscv/include/rte_atomic.h:
Using rte_smp_[r/w]mb
Warning in lib/eal/riscv/include/rte_atomic.h:
Using __atomic_thread_fence