Test-Label: Intel-compilation
Test-Status: FAILURE
http://dpdk.org/patch/56046

_apply issues_

Submitter: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
Date: 2019-07-03 16:52:20
Reply_mail: 20190703165220.1068-1-pbhagavatula@marvell.com
DPDK git baseline:
	Repo:dpdk, CommitID: c0ed103a027385f14f352d46ff5450826b2746b7

*Repo: dpdk
* CASP inline-asm. i.e. if the optimization level is reduced to -O0 the
 * CASP restrictions aren't followed and the compiler might end up violation the
 * CASP rules. Fix it by explicitly providing ((optimize("-O3"))).
 *
 * Example:
 * ccSPMGzq.s:1648: Error: reg pair must start from even reg at
 * operand 1 - `casp x21,x22,x0,x1,[x19]'
 */
static  __attribute__((optimize("-O3"))) __rte_noinline int __hot
npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,
			  unsigned int n, void **obj_table)
{
	const __uint128_t wdata128 = ((__uint128_t)wdata << 64) | wdata;
	uint64x2_t failed = vdupq_n_u64(~0);

	switch (n) {
	case 32:
	{
		__uint128_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
--
		"fmov v18.D[1], %H[t2]\n"
		"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
		"fmov d19, %[t3]\n"
		"fmov v19.D[1], %H[t3]\n"
		"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"and %[failed].16B, %[failed].16B, v17.16B\n"
		"and %[failed].16B, %[failed].16B, v18.16B\n"
		"and %[failed].16B, %[failed].16B, v19.16B\n"
		"fmov d20, %[t4]\n"
		"fmov v20.D[1], %H[t4]\n"
		"fmov d21, %[t5]\n"
		"fmov v21.D[1], %H[t5]\n"
		"fmov d22, %[t6]\n"
		"fmov v22.D[1], %H[t6]\n"
		"fmov d23, %[t7]\n"
		"fmov v23.D[1], %H[t7]\n"
		"and %[failed].16B, %[failed].16B, v20.16B\n"
		"and %[failed].16B, %[failed].16B, v21.16B\n"
		"and %[failed].16B, %[failed].16B, v22.16B\n"
		"and %[failed].16B, %[failed].16B, v23.16B\n"
		"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
		"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
		"fmov d16, %[t8]\n"
		"fmov v16.D[1], %H[t8]\n"
		"fmov d17, %[t9]\n"
		"fmov v17.D[1], %H[t9]\n"
		"fmov d18, %[t10]\n"
		"fmov v18.D[1], %H[t10]\n"
		"fmov d19, %[t11]\n"
		"fmov v19.D[1], %H[t11]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"and %[failed].16B, %[failed].16B, v17.16B\n"
		"and %[failed].16B, %[failed].16B, v18.16B\n"
		"and %[failed].16B, %[failed].16B, v19.16B\n"
		"fmov d20, %[t0]\n"
		"fmov v20.D[1], %H[t0]\n"
		"fmov d21, %[t1]\n"
		"fmov v21.D[1], %H[t1]\n"
		"fmov d22, %[t2]\n"
		"fmov v22.D[1], %H[t2]\n"
		"fmov d23, %[t3]\n"
		"fmov v23.D[1], %H[t3]\n"
		"and %[failed].16B, %[failed].16B, v20.16B\n"
		"and %[failed].16B, %[failed].16B, v21.16B\n"
		"and %[failed].16B, %[failed].16B, v22.16B\n"
		"and %[failed].16B, %[failed].16B, v23.16B\n"
		"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
		"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
		: "+Q" (*addr), [failed] "=&w" (failed),
		[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
		[t3] "=&r" (t3), [t4] "=&r" (t4), [t5] "=&r" (t5),
		[t6] "=&r" (t6), [t7] "=&r" (t7), [t8] "=&r" (t8),
		[t9] "=&r" (t9), [t10] "=&r" (t10), [t11] "=&r" (t11)
		: [wdata] "r" (wdata128), [dst] "r" (obj_table),
--
		"fmov v17.D[1], %H[t1]\n"
		"fmov d18, %[t2]\n"
		"fmov v18.D[1], %H[t2]\n"
		"fmov d19, %[t3]\n"
		"fmov v19.D[1], %H[t3]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"and %[failed].16B, %[failed].16B, v17.16B\n"
		"and %[failed].16B, %[failed].16B, v18.16B\n"
		"and %[failed].16B, %[failed].16B, v19.16B\n"
		"fmov d20, %[t4]\n"
		"fmov v20.D[1], %H[t4]\n"
		"fmov d21, %[t5]\n"
		"fmov v21.D[1], %H[t5]\n"
		"fmov d22, %[t6]\n"
		"fmov v22.D[1], %H[t6]\n"
		"fmov d23, %[t7]\n"
		"fmov v23.D[1], %H[t7]\n"
		"and %[failed].16B, %[failed].16B, v20.16B\n"
		"and %[failed].16B, %[failed].16B, v21.16B\n"
		"and %[failed].16B, %[failed].16B, v22.16B\n"
		"and %[failed].16B, %[failed].16B, v23.16B\n"
		"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
		"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
		: "+Q" (*addr), [failed] "=&w" (failed),
		[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
		[t3] "=&r" (t3), [t4] "=&r" (t4), [t5] "=&r" (t5),
		[t6] "=&r" (t6), [t7] "=&r" (t7)
		: [wdata] "r" (wdata128), [dst] "r" (obj_table),
		[loc] "r" (addr)
--
		"fmov v17.D[1], %H[t1]\n"
		"fmov d18, %[t2]\n"
		"fmov v18.D[1], %H[t2]\n"
		"fmov d19, %[t3]\n"
		"fmov v19.D[1], %H[t3]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"and %[failed].16B, %[failed].16B, v17.16B\n"
		"and %[failed].16B, %[failed].16B, v18.16B\n"
		"and %[failed].16B, %[failed].16B, v19.16B\n"
		"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
		: "+Q" (*addr), [failed] "=&w" (failed),
		[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
		[t3] "=&r" (t3)
		: [wdata] "r" (wdata128), [dst] "r" (obj_table),
		[loc] "r" (addr)
		: "memory", "v16", "v17", "v18", "v19"
--
		"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
		"fmov d16, %[t0]\n"
		"fmov v16.D[1], %H[t0]\n"
		"fmov d17, %[t1]\n"
		"fmov v17.D[1], %H[t1]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"and %[failed].16B, %[failed].16B, v17.16B\n"
		"st1 { v16.2d, v17.2d}, [%[dst]], 32\n"
		: "+Q" (*addr), [failed] "=&w" (failed),
		[t0] "=&r" (t0), [t1] "=&r" (t1)
		: [wdata] "r" (wdata128), [dst] "r" (obj_table),
		[loc] "r" (addr)
		: "memory", "v16", "v17"
		);
--
		asm volatile (
		".cpu  generic+lse\n"
		"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
		"fmov d16, %[t0]\n"
		"fmov v16.D[1], %H[t0]\n"
		"and %[failed].16B, %[failed].16B, v16.16B\n"
		"st1 { v16.2d}, [%[dst]], 16\n"
		: "+Q" (*addr), [failed] "=&w" (failed),
		[t0] "=&r" (t0)
		: [wdata] "r" (wdata128), [dst] "r" (obj_table),
		[loc] "r" (addr)
		: "memory", "v16"
		);
		break;
	}

error: patch failed: drivers/mempool/octeontx2/otx2_mempool_ops.c:54
error: drivers/mempool/octeontx2/otx2_mempool_ops.c: patch does not apply

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