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[204.195.112.199]) by smtp.gmail.com with ESMTPSA id s15-20020a63524f000000b003c14af5062dsm1745391pgl.69.2022.05.18.10.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 10:04:06 -0700 (PDT) Date: Wed, 18 May 2022 10:04:04 -0700 From: Stephen Hemminger <stephen@networkplumber.org> To: "Sanford, Robert" <rsanford@akamai.com> Cc: Antonio Di Bacco <a.dibacco.ks@gmail.com>, "users@dpdk.org" <users@dpdk.org> Subject: Re: DPDK performances surprise Message-ID: <20220518100404.2cb93c04@hermes.local> In-Reply-To: <E413B821-D2F6-476F-B25B-4105FB0D25C2@akamai.com> References: <CAO8pfFnSf070rr3n5LXwY9cSB0jFYF_3ENmVRH8q_AaBBKoJ=w@mail.gmail.com> <E413B821-D2F6-476F-B25B-4105FB0D25C2@akamai.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK usage discussions <users.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/users>, <mailto:users-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/users/> List-Post: <mailto:users@dpdk.org> List-Help: <mailto:users-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/users>, <mailto:users-request@dpdk.org?subject=subscribe> Errors-To: users-bounces@dpdk.org On Wed, 18 May 2022 16:53:04 +0000 "Sanford, Robert" <rsanford@akamai.com> wrote: > My guess is that most of the packet data has a short life in the L3 cache (before being overwritten by newer packets), but is never flushed to memory. > > From: Antonio Di Bacco <a.dibacco.ks@gmail.com> > Date: Wednesday, May 18, 2022 at 12:40 PM > To: "users@dpdk.org" <users@dpdk.org> > Subject: DPDK performances surprise > > I recently read a performance test where l2fwd was able to receive packets (8000B) from a 100 Gbps card, swap the L2 addresses and send them back to the same port to be received by an ethernet analyzer. The throughput achieved was close to 100 Gbps on a XEON machine (Intel(R) Xeon(R) Platinum 8176 CPU @ 2.10GHz) . This is the same processor I have and I know that, if I try to write around 8000B to the attached DDR4 (2666MT/s) on an allocated 1GB hugepage, I get a maximum throughput of around 20GB/s. > > Now, a 100 Gbps can generate a flow of around 12 GB/s, these packets have to be written to the DDR and then read back to swap L2 addresses and this leads to a cumulative bandwidth on the DDR that is around 2x12 GB/s and is more than the 20GB/s of available bandwidth on the DDR4. > > How can this be possible ? Likely cache effects from DDIO. What is your packet size.