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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e9a5f5fa55sm1644215a91.17.2024.11.07.08.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 08:13:08 -0800 (PST) Date: Thu, 7 Nov 2024 08:13:07 -0800 From: Stephen Hemminger To: "Wieckowski, Jacob" Cc: Dmitry Kozlyuk , "users@dpdk.org" Subject: Re: DMA Transfers to PCIe Bar Memory Message-ID: <20241107081307.51902773@hermes.local> In-Reply-To: References: <20241106204604.444529d5@sovereign> <20241107124225.50c22ee2@sovereign> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org On Thu, 7 Nov 2024 13:09:41 +0000 "Wieckowski, Jacob" wrote: > Hi Jacob, > > 2024-11-07 11:50 (UTC+0000), Wieckowski, Jacob: > > Hi Dimitry, > > > > I am sorry, I was a bit too far ahead with my thoughts. > > > > We have started a DPDK evaluation project to build knowledge and understanding of the DPDK framework. > > We used an E1000 driver with a workaround to gain access to the PCIe 5.0 R-Tile on the Intel Agilex7 FPGA under Windows. > > > > Accesses to the PCIe BAR work in principle, but we can currently only carry out 64-bit accesses to the BAR memory. > > In the PCIe Config Space in the Capabilities Register, a maximum payload size of 512 bytes is configured. > > The Intel Core in the FPGA and the Root Complex also support TLPs of this length. > > > > We use the rte_read32 and rte_write32 functions to access the bar memory, which obviously executes accesses with max 2 DWs. > > We were able to trigger this in the FPGA because only TLP with length 2 arrived on the RX Interface. > > > > How can a block transfer be initiated in DPDK so that TLPs with a length of 128 DWs are generated on the PCIe Bus? > > Thanks, now I understand what you need. > Unfortunately DPDK has no relevant API; rte_read**() is for small registers. > Maybe there's some useful code in "drivers/raw", but this area is completely unknown to me, sorry. > Try replying with what you wrote above to the thread in users@dpdk.org and Cc: Intel people from MAINTAINERS file responsible for "drivers/raw". In general, direct access to PCI by applications is discouraged. All PCI access should be in driver code. What you describe is a bug in the E1000 driver, and should fixed there.