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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: tietoevry.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8199.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fce33fc6-c398-4d97-3108-08dce2fbe75a X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Oct 2024 16:04:32.5859 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: cbede638-a3d9-459f-8f4e-24ced73b4e5e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pc4CWwN6/Tw1dhEURVN9iOdr4OvM82cIgY7onhM/EuoChInGCGadtVP7WDiHZMHg1qQvS9VgCBqgCUMMPF1AA6ZM90Mv4Oyuvzgz+8mNgQo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7167 X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org Hi! Thanks for the response.=20 I think I get the descriptor part, but what is the relation to queues? If t= he hardware supports 1024 descriptors and I need 6 queues, do I have 1024 d= escriptors on each TX queue?=20 / Mikael -----Original Message----- From: Stephen Hemminger =20 Sent: Wednesday, October 2, 2024 5:29 PM To: Mikael R Carlsson Cc: users@dpdk.org Subject: Re: Relation between DPDK queue and descriptors On Wed, 2 Oct 2024 15:21:45 +0000 Mikael R Carlsson wrote: > Hi experts! >=20 > I have a hard time to finds a good documentation about the relation betwe= en DPDK TX queue and descriptors. >=20 > Queue as in rte_eth_tx_queue_setup > Descriptor as in rte_eth_dev_adjust_nb_rx_rx_desc >=20 > We suspect we run out of descriptors in TX path, we are not sure here. We= use more than one TX queue. Will we get more descriptors if we only use on= e single TX queue? Does anyone know if there is some good documentation reg= arding the TX queue and the descriptors? >=20 > / Mikael >=20 A typical driver has a hardware ring buffer between the driver and the hard= ware. One ring for transmit, and another for receive. The entries in the ring are hardware specific data structure called descrip= tors. Each descriptor usually has physical memory address, size, and flags. The number of Rx descriptors determines the number of unread frames the dri= ver can hold. Too small, and you risk dropping packets; too large and under= stress load the driver can end up buffering excessively causing latency (b= ufferbloat). Similar on Tx but less of a problem because typically the network is faster= than the application can send packets.