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 <20230609114009.344257-1-getelson@nvidia.com>
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From: omer yamac <aomeryamac@gmail.com>
Date: Sat, 10 Jun 2023 20:52:42 +0300
Message-ID: <CA+sj1i9DHNj_AevyEFt9asv4bMq6_DOEMWnXEsQvB=Dd4RBDnw@mail.gmail.com>
Subject: Re: rte_flow_type_integrity example for checksum correctness
To: Gregory Etelson <getelson@nvidia.com>
Cc: aisenur.yoldas@b-ulltech.com, users@dpdk.org
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Hi,
I just wonder why do you need a Mellanox? As I understood, you are reading
pcap file and you may check below link
https://doc.dpdk.org/guides/nics/pcap_ring.html


On Fri, Jun 9, 2023, 2:40 PM Gregory Etelson <getelson@nvidia.com> wrote:

> Hello Aisenur,
>
> Flow integrity support in MLX5 PMD starts with  ConnectX-6 Dx
>
> Regards,
> Gregory
>

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<div dir=3D"auto">Hi,=C2=A0<div dir=3D"auto">I just wonder why do you need =
a Mellanox? As I understood, you are reading pcap file and you may check be=
low link</div><div dir=3D"auto"><a href=3D"https://doc.dpdk.org/guides/nics=
/pcap_ring.html">https://doc.dpdk.org/guides/nics/pcap_ring.html</a><br></d=
iv><div dir=3D"auto"><br></div></div><br><div class=3D"gmail_quote"><div di=
r=3D"ltr" class=3D"gmail_attr">On Fri, Jun 9, 2023, 2:40 PM Gregory Etelson=
 &lt;<a href=3D"mailto:getelson@nvidia.com" target=3D"_blank" rel=3D"norefe=
rrer">getelson@nvidia.com</a>&gt; wrote:<br></div><blockquote class=3D"gmai=
l_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left=
:1ex">Hello Aisenur,<br>
<br>
Flow integrity support in MLX5 PMD starts with=C2=A0 ConnectX-6 Dx<br>
<br>
Regards,<br>
Gregory<br>
</blockquote></div>

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