From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C6ED46463 for ; Mon, 24 Mar 2025 08:34:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0FC940268; Mon, 24 Mar 2025 08:34:01 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id E637740151 for ; Mon, 24 Mar 2025 08:33:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1742801639; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9N8PNGfdrA769Zqfiyw1Ap5o84sYXUD1CB5n4rRhrXU=; b=OpsUaHyyIFXUKfAq8kH5iMKLoVHwTnUBkKBTxRZps6ooea1rH3N9CE394e+v52VTxGPAVZ LWHnupXVITlCUCNPucEuZiYgvG8+saGy802uGrcw5ofnV2q29NfppruNkvJGbsLJCC6Qwb DvaC12NfyWfXP1eeWWtnetysWTkgXOY= Received: from mail-lj1-f198.google.com (mail-lj1-f198.google.com [209.85.208.198]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-642-eLSdllbcOoSuQxyf3JKHTg-1; Mon, 24 Mar 2025 03:33:57 -0400 X-MC-Unique: eLSdllbcOoSuQxyf3JKHTg-1 X-Mimecast-MFC-AGG-ID: eLSdllbcOoSuQxyf3JKHTg_1742801636 Received: by mail-lj1-f198.google.com with SMTP id 38308e7fff4ca-30c4fd96a7bso18773191fa.3 for ; Mon, 24 Mar 2025 00:33:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742801636; x=1743406436; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9N8PNGfdrA769Zqfiyw1Ap5o84sYXUD1CB5n4rRhrXU=; b=STvEOjTB46x4m+pY14iB4GUSuThb6o1FG5BAlygf4WvXb4FNpfATn97J01IkGa6hOB mx6PAacI3fTCrJI98OYqkpFAwtlrJDrRf2Q0USOaakIleopHawnOOak9ccWpMzJnLGd3 igtdhJEptSJj14QeBWM+vblvfuXpB5b/fL7ojNoxHPOBs2DMNvsUo5p2upNC6Iatpg4Q yCWnk0Gf7TZWi4W4AX+tVPFlzBXrU6Wcnw1k+km05T1jVdh4ozkqIUuyT3jDcyHjP4uL Wt7rmjc6vfIqewSc/8YjbdKFzPCacBEPqEUxtPy+xqAKCxrmJ//b4Cv9VyAPWvMCzOAg hSqw== X-Gm-Message-State: AOJu0YwM9dRA4csHtpvw9OowQiPbcmfMflc1ikgdumMim0oRBqGMDorB LuEGpPjudSjhuxwOMKK7gqNt0UZcox+GmLJapAv3K2zFhFcYha3zslqm3BIcsV5LEWAC1IWqx0g QhBxfZ747feokIGrO2Nndp5zT1aOHA1JcHDMJaHUnHX1aA7bRaVNz6mrvmf4Syk7GqSzj1V/L4+ zgpJyXF/v8IUqM1TFQ+A== X-Gm-Gg: ASbGncshYCk9Lcm893BHDp/Uw6up6cwn4CAKoyw9se5kYn6/m+aPhJZho6xSTDrOXSq 3dzUW3tBHp48ds0bCqMXRlcV0qIbC4q06ZkcSiJO5CZBhFbqmJx+lpaZx49WO+/TGMZwIUOAmgB s= X-Received: by 2002:a2e:bea4:0:b0:30b:c3ce:ea46 with SMTP id 38308e7fff4ca-30d7e2055e2mr42931871fa.5.1742801635983; Mon, 24 Mar 2025 00:33:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEv7hB2v3MWKKsOo9/43IogU1m5KQo0lje/HVnXyUm37Zzw53uCguyG/HHKFUMx6NRiKYOwIpo2mLmHlDBeNkM= X-Received: by 2002:a2e:bea4:0:b0:30b:c3ce:ea46 with SMTP id 38308e7fff4ca-30d7e2055e2mr42931701fa.5.1742801635620; Mon, 24 Mar 2025 00:33:55 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: David Marchand Date: Mon, 24 Mar 2025 08:33:43 +0100 X-Gm-Features: AQ5f1Jpla2nqH_fbTF7A56veCqiTEdj1jZz0BIN16FXv1u06hZOhTWxpck0tpPY Message-ID: Subject: Re: Intel 800/700 series support for RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP? To: Trey Harrison , Bruce Richardson , "Burakov, Anatoly" , Vladimir Medvedkin , Ian Stokes Cc: users@dpdk.org X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: g3g9uqgLp5_rgc8G3Wdm_OH5ezl5gS8TH9UPws_ptcg_1742801636 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org On Sat, Mar 22, 2025 at 5:37=E2=80=AFAM Trey Harrison wrote: > > It seems that there is no support for > RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP on Intel's 700/800 series chips > in any DPDK release (although, there is support for the 225/226 > chips). I have done as thorough of a search on this as I can, but > wanted to reach out to actual devs before giving up. > > I guess I am hoping to simply confirm, from anyone with knowledge of > the subject, that there is in fact no such support in any forthcoming > patches / DPDK releases / driver revisions / etc. > > It would also be interesting to know whether the hardware is even > capable of this feature - if so, maybe it would not be too complicated > to implement it? Especially since there is an example in net/igc to > work from.. Adding Intel maintainers in the loop. --=20 David Marchand