From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2866FA0503 for ; Thu, 19 May 2022 11:04:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B1A540150; Thu, 19 May 2022 11:04:19 +0200 (CEST) Received: from mail-oa1-f50.google.com (mail-oa1-f50.google.com [209.85.160.50]) by mails.dpdk.org (Postfix) with ESMTP id E91C840140 for ; Thu, 19 May 2022 11:04:17 +0200 (CEST) Received: by mail-oa1-f50.google.com with SMTP id 586e51a60fabf-d6e29fb3d7so5981268fac.7 for ; Thu, 19 May 2022 02:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=R48MkyayJgoOhLhRtCl+V/QMtryI6Y7s3qArakyQvz8=; b=Q63cLJBqvtksI3SVrYsDWXzc8a/083Ivb1neqjGV1OgKBw8kLX8ja3i6cLETnzpy51 u2LVcwtICoqZyc+D0Jv0EtXcphIluSKrdiapsk28LVcgmX4GNltGrOgTMEskFTpRlHuF hVVGlRu1UMx0GY439zW+WTRLx3aRp13/StrRr7AlIFyfipKPjwP+sHolKAgsXlq0YzFv W8CgwT9e3iDT9j8rzM3BtvZf0VoXmIDE4ZnUOEXPF4VGCjJ5xvtaQx/tSHOW/MUeAEQQ yKbXothUtQs5AcLTQD6fGlcULKZNFN44vovEPL4ftVX7CXUGyZETnpNdbN5qUYeJf9sQ HtGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=R48MkyayJgoOhLhRtCl+V/QMtryI6Y7s3qArakyQvz8=; b=7zpah6VZwmXJv8e+WVw8rpMCdbQS+2HvoxLkiV+2biNu+1e/1GCCsZoxAC40SnQIob REyFOo8xabkZPiIB/y5nkJ8NhUswN/tffyYrRQKomorzZ4r+gjRYUIVrScMDXC9jcwxu mW45GlYV8Xpwp6PPi3sT/oaZS5AfTEbKkTSWbzWUsEW87yGmPjb0fIHcIOFkMCnvQ1EM MVHipAQQ5dO32J21FvU6w8tp25RiO3AYxxfznKly4bbGkCV7SGuMnT0PXZrR5ZBJz7/v ofLfr+HKXzk7jeLeLMK8CA8A/ZsIcIZwvtDFkwxaC4xUJnZZqkWOu8J82cbc8mC5arOo vhlw== X-Gm-Message-State: AOAM531gRr81Q7sBTgxvsXbsoyxr4pfPfnewqR9YlGCV/NN+qFxOAr/g EaB2Ky4Csw1Hp2CqXy0cOSyR15xJ3196lCIKZz4= X-Google-Smtp-Source: ABdhPJwz2CaxfSS8RZqHgkmuHqyfWcQmUsc/6eJ0y8LCN6Tpx1oXTkGc+M1FDASitd8Me3ueAqffToTEmCm0rYAzfko= X-Received: by 2002:a05:6870:b686:b0:dc:a9f4:90a2 with SMTP id cy6-20020a056870b68600b000dca9f490a2mr2412582oab.243.1652951055883; Thu, 19 May 2022 02:04:15 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Antonio Di Bacco Date: Thu, 19 May 2022 11:04:04 +0200 Message-ID: Subject: Re: DPDK performances surprise To: "Kinsella, Ray" Cc: "Sanford, Robert" , "users@dpdk.org" Content-Type: multipart/alternative; boundary="00000000000084616005df59a8b7" X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org --00000000000084616005df59a8b7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable This tool seems awesome!!! Better than VTUNE? On Thu, May 19, 2022 at 10:29 AM Kinsella, Ray wrote: > I=E2=80=99d say that is likely yes. > > > > FYI - pcm-memory is very handy tool for looking at memory traffic. > > https://github.com/opcm/pcm > > > > Thanks, > > > > Ray K > > > > *From:* Sanford, Robert > *Sent:* Wednesday 18 May 2022 17:53 > *To:* Antonio Di Bacco ; users@dpdk.org > *Subject:* Re: DPDK performances surprise > > > > My guess is that most of the packet data has a short life in the L3 cache > (before being overwritten by newer packets), but is never flushed to memo= ry. > > > > *From: *Antonio Di Bacco > *Date: *Wednesday, May 18, 2022 at 12:40 PM > *To: *"users@dpdk.org" > *Subject: *DPDK performances surprise > > > > I recently read a performance test where l2fwd was able to receive packet= s > (8000B) from a 100 Gbps card, swap the L2 addresses and send them back to > the same port to be received by an ethernet analyzer. The throughput > achieved was close to 100 Gbps on a XEON machine (Intel(R) Xeon(R) Platin= um > 8176 CPU @ 2.10GHz) . This is the same processor I have and I know that, = if > I try to write around 8000B to the attached DDR4 (2666MT/s) on an allocat= ed > 1GB hugepage, I get a maximum throughput of around 20GB/s. > > > > Now, a 100 Gbps can generate a flow of around 12 GB/s, these packets have > to be written to the DDR and then read back to swap L2 addresses and this > leads to a cumulative bandwidth on the DDR that is around 2x12 GB/s and i= s > more than the 20GB/s of available bandwidth on the DDR4. > > > > How can this be possible ? > --00000000000084616005df59a8b7 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
This tool seems awesome!!! Better than VTUNE?

On Thu, May 1= 9, 2022 at 10:29 AM Kinsella, Ray <ray.kinsella@intel.com> wrote:

I=E2=80=99d say that is likely yes.

=C2=A0

FYI - pcm-memory is very handy tool for looking at memory tr= affic.

ht= tps://github.com/opcm/pcm

=C2=A0

Thanks,

=C2=A0

Ray K

=C2=A0

F= rom: Sanford, Robert <rsanford@akamai.com>
Sent: Wednesday 18 May 2022 17:53
To: Antonio Di Bacco <a.dibacco.ks@gmail.com>; users@dpdk.org
Subject: Re: DPDK performances surprise

=C2=A0

My guess is that most of the packet data has a short l= ife in the L3 cache (before being overwritten by newer packets), but is nev= er flushed to memory.

=C2=A0

From: Antoni= o Di Bacco <= a.dibacco.ks@gmail.com>
Date: Wednesday, May 18, 2022 at 12:40 PM
To: "users@= dpdk.org" <= users@dpdk.org>
Subject: DPDK performances surprise

<= /u>=C2=A0

I re= cently read a performance test where l2fwd was able to receive=C2=A0packets= (8000B) from a 100 Gbps card, swap the L2 addresses and send them back to = the same port to be received by an ethernet analyzer. The throughput achieved was close to 100 Gbps on a XEON machine = (Intel(R) Xeon(R) Platinum 8176 CPU @ 2.10GHz) . This is the same processor= I have and I know that, if I try to write around 8000B to the attached DDR= 4 (2666MT/s) on an allocated 1GB hugepage, I get a maximum throughput of around 20GB/s.=C2=A0

<= /u>=C2=A0

Now,= a 100 Gbps can generate a flow of around 12 GB/s, these packets have to be= written to the DDR and then read back to swap L2 addresses and this leads = to a cumulative bandwidth on the DDR that is around 2x12 GB/s and is more than the 20GB/s of available bandwidt= h on the DDR4.=C2=A0

<= /u>=C2=A0

How = can this be possible ?=C2=A0

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