From: Wenzhuo Lu <wenzhuo.lu@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 10/26] ixgbe/base: add logic to reset CS4227 when needed
Date: Fri, 5 Jun 2015 13:21:42 +0800 [thread overview]
Message-ID: <1433481718-24253-11-git-send-email-wenzhuo.lu@intel.com> (raw)
In-Reply-To: <1433481718-24253-1-git-send-email-wenzhuo.lu@intel.com>
On some hardware platforms, the CS4227 does not initialize properly.
Detect those cases and reset it appropriately.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
---
drivers/net/ixgbe/base/ixgbe_phy.h | 12 +++
drivers/net/ixgbe/base/ixgbe_x550.c | 184 ++++++++++++++++++++++++++++++++++++
2 files changed, 196 insertions(+)
diff --git a/drivers/net/ixgbe/base/ixgbe_phy.h b/drivers/net/ixgbe/base/ixgbe_phy.h
index 7456bf4..ba5b308 100644
--- a/drivers/net/ixgbe/base/ixgbe_phy.h
+++ b/drivers/net/ixgbe/base/ixgbe_phy.h
@@ -83,9 +83,21 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
#define IXGBE_CS4227 0xBE /* CS4227 address */
+#define IXGBE_CS4227_GLOBAL_ID_LSB 0
+#define IXGBE_CS4227_SCRATCH 2
+#define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5
+#define IXGBE_CS4227_SCRATCH_VALUE 0x5aa5
+#define IXGBE_CS4227_RETRIES 5
#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
#define IXGBE_CS4227_EDC_MODE_SR 0x0004
+#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */
+#define IXGBE_CS4227_RESET_DELAY 500 /* milliseconds */
+#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */
+#define IXGBE_PE 0xE0 /* Port expander address */
+#define IXGBE_PE_OUTPUT 1 /* Output register offset */
+#define IXGBE_PE_CONFIG 3 /* Config register offset */
+#define IXGBE_PE_BIT1 (1 << 1)
/* Flow control defines */
#define IXGBE_TAF_SYM_PAUSE 0x400
diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c
index 0ce1c85..c91e737 100644
--- a/drivers/net/ixgbe/base/ixgbe_x550.c
+++ b/drivers/net/ixgbe/base/ixgbe_x550.c
@@ -38,6 +38,7 @@ POSSIBILITY OF SUCH DAMAGE.
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
+
/**
* ixgbe_init_ops_X550 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
@@ -82,6 +83,187 @@ s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
}
/**
+ * ixgbe_read_cs4227 - Read CS4227 register
+ * @hw: pointer to hardware structure
+ * @reg: register number to write
+ * @value: pointer to receive value read
+ *
+ * Returns status code
+ **/
+STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
+{
+ return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
+}
+
+/**
+ * ixgbe_write_cs4227 - Write CS4227 register
+ * @hw: pointer to hardware structure
+ * @reg: register number to write
+ * @value: value to write to register
+ *
+ * Returns status code
+ **/
+STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
+{
+ return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
+}
+
+/**
+ * ixgbe_get_cs4227_status - Return CS4227 status
+ * @hw: pointer to hardware structure
+ *
+ * Returns error if CS4227 not successfully initialized
+ **/
+STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
+{
+ s32 status;
+ u16 value = 0;
+ u8 retry;
+
+ for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
+ status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
+ &value);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
+ break;
+ msec_delay(IXGBE_CS4227_CHECK_DELAY);
+ }
+ if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
+ return IXGBE_ERR_PHY;
+
+ status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
+ IXGBE_CS4227_SCRATCH_VALUE);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ if (value != IXGBE_CS4227_SCRATCH_VALUE)
+ return IXGBE_ERR_PHY;
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_read_pe - Read register from port expander
+ * @hw: pointer to hardware structure
+ * @reg: register number to read
+ * @value: pointer to receive read value
+ *
+ * Returns status code
+ **/
+STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
+{
+ s32 status;
+
+ status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
+ if (status != IXGBE_SUCCESS)
+ ERROR_REPORT2(IXGBE_ERROR_CAUTION,
+ "port expander access failed with %d\n", status);
+ return status;
+}
+
+/**
+ * ixgbe_write_pe - Write register to port expander
+ * @hw: pointer to hardware structure
+ * @reg: register number to write
+ * @value: value to write
+ *
+ * Returns status code
+ **/
+STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
+{
+ s32 status;
+
+ status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
+ if (status != IXGBE_SUCCESS)
+ ERROR_REPORT2(IXGBE_ERROR_CAUTION,
+ "port expander access failed with %d\n", status);
+ return status;
+}
+
+/**
+ * ixgbe_reset_cs4227 - Reset CS4227 using port expander
+ * @hw: pointer to hardware structure
+ *
+ * Returns error code
+ **/
+STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
+{
+ s32 status;
+ u8 reg;
+
+ status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ reg |= IXGBE_PE_BIT1;
+ status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
+ if (status != IXGBE_SUCCESS)
+ return status;
+
+ status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ reg &= ~IXGBE_PE_BIT1;
+ status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
+ if (status != IXGBE_SUCCESS)
+ return status;
+
+ status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ reg &= ~IXGBE_PE_BIT1;
+ status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
+ if (status != IXGBE_SUCCESS)
+ return status;
+
+ usec_delay(IXGBE_CS4227_RESET_HOLD);
+
+ status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
+ if (status != IXGBE_SUCCESS)
+ return status;
+ reg |= IXGBE_PE_BIT1;
+ status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
+ if (status != IXGBE_SUCCESS)
+ return status;
+
+ msec_delay(IXGBE_CS4227_RESET_DELAY);
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_check_cs4227 - Check CS4227 and reset as needed
+ * @hw: pointer to hardware structure
+ **/
+STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
+{
+ u32 swfw_mask = hw->phy.phy_semaphore_mask;
+ s32 status;
+ u8 retry;
+
+ for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
+ status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
+ if (status != IXGBE_SUCCESS) {
+ ERROR_REPORT2(IXGBE_ERROR_CAUTION,
+ "semaphore failed with %d\n", status);
+ return;
+ }
+ status = ixgbe_get_cs4227_status(hw);
+ if (status == IXGBE_SUCCESS) {
+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
+ msec_delay(hw->eeprom.semaphore_delay);
+ return;
+ }
+ ixgbe_reset_cs4227(hw);
+ hw->mac.ops.release_swfw_sync(hw, swfw_mask);
+ msec_delay(hw->eeprom.semaphore_delay);
+ }
+ ERROR_REPORT2(IXGBE_ERROR_CAUTION,
+ "Unable to initialize CS4227, err=%d\n", status);
+}
+
+/**
* ixgbe_identify_phy_x550em - Get PHY type based on device id
* @hw: pointer to hardware structure
*
@@ -103,6 +285,8 @@ STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
+ ixgbe_check_cs4227(hw);
+
return ixgbe_identify_module_generic(hw);
break;
case IXGBE_DEV_ID_X550EM_X_KX4:
--
1.9.3
next prev parent reply other threads:[~2015-06-05 5:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-05 5:21 [dpdk-dev] [PATCH 00/26] update ixgbe base driver Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 01/26] ixgbe/base: update copyright and readme Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 02/26] ixgbe/base: fix code comment, double from Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 03/26] ixgbe/base: fix typo error in code comment Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 04/26] ixgbe/base: check return value after calling Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 05/26] ixgbe/base: allow tunneled UDP and TCP frames to reach their destination Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 06/26] ixgbe/base: erase ixgbe_get_hi_status Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 07/26] ixgbe/base: provide unlocked I2C methods Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 08/26] ixgbe/base: reduce I2C retry count on X550 devices Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 09/26] ixgbe/base: issue firmware command when coming up Wenzhuo Lu
2015-06-05 5:21 ` Wenzhuo Lu [this message]
2015-06-05 5:21 ` [dpdk-dev] [PATCH 11/26] ixgbe/base: restore ESDP settings after MAC reset Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 12/26] ixgbe/base: disable FEC(Forward Error Correction) to save power Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 13/26] ixgbe/base: set lan_id for non-PCIe devices Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 14/26] ixgbe/base: add SFP+ dual-speed support Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 15/26] ixgbe/base: add SW based LPLU support Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 16/26] ixgbe/base: fix flow control for KR backplane Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 17/26] ixgbe/base: new simplified x550em init flow Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 18/26] ixgbe/base: move I2C MUX function from ixgbe_x540.c to ixgbe_x550.c Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 19/26] ixgbe/base: change return value for ixgbe_setup_internal_phy_t_x550em Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 20/26] ixgbe/base: ixgbe_setup_internal_phy_x550em function clean-up Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 21/26] ixgbe/base: add x550em Auto neg Flow Control support Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 22/26] ixgbe/base: add x550em PHY interrupt and forced 1G/10G support Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 23/26] ixgbe/base: add link check support for x550em PHY Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 24/26] ixgbe/base: set lan_id before first I2C access Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 25/26] ixgbe/base: added x550em PHY reset function Wenzhuo Lu
2015-06-05 5:21 ` [dpdk-dev] [PATCH 26/26] ixgbe/base: block EEE(Energy Efficient Ethernet) setup on the interfaces that don't support EEE Wenzhuo Lu
2015-06-09 4:10 ` [dpdk-dev] [PATCH 00/26] update ixgbe base driver Zhang, Helin
2015-06-15 20:49 ` Thomas Monjalon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1433481718-24253-11-git-send-email-wenzhuo.lu@intel.com \
--to=wenzhuo.lu@intel.com \
--cc=dev@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).