From: Jingjing Wu <jingjing.wu@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 17/52] i40e/base: create new BIT and BIT_ULL macros
Date: Sun, 6 Sep 2015 15:11:31 +0800 [thread overview]
Message-ID: <1441523526-26202-18-git-send-email-jingjing.wu@intel.com> (raw)
In-Reply-To: <1441523526-26202-1-git-send-email-jingjing.wu@intel.com>
Use macros for abstracting (1 << foo) to BIT(foo)
and (1ULL << foo64) to BIT_ULL(foo64) in order to match
better with linux kernel requirements.
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/i40e/base/i40e_common.c | 4 ++--
drivers/net/i40e/base/i40e_dcb.h | 8 ++++----
drivers/net/i40e/base/i40e_diag.c | 11 ++++-------
drivers/net/i40e/base/i40e_hmc.h | 6 +++---
drivers/net/i40e/base/i40e_lan_hmc.c | 24 ++++++++++++------------
drivers/net/i40e/base/i40e_nvm.c | 6 +++---
drivers/net/i40e/base/i40e_type.h | 25 +++++++++++++++----------
7 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 8c8c4a9..8c96f5f 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1393,9 +1393,9 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
blink = false;
if (blink)
- gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
+ gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
else
- gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
+ gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
break;
diff --git a/drivers/net/i40e/base/i40e_dcb.h b/drivers/net/i40e/base/i40e_dcb.h
index 2d4a3d0..841cfc3 100644
--- a/drivers/net/i40e/base/i40e_dcb.h
+++ b/drivers/net/i40e/base/i40e_dcb.h
@@ -74,9 +74,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I40E_IEEE_ETS_MAXTC_SHIFT 0
#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
#define I40E_IEEE_ETS_CBS_SHIFT 6
-#define I40E_IEEE_ETS_CBS_MASK (0x1 << I40E_IEEE_ETS_CBS_SHIFT)
+#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
#define I40E_IEEE_ETS_WILLING_SHIFT 7
-#define I40E_IEEE_ETS_WILLING_MASK (0x1 << I40E_IEEE_ETS_WILLING_SHIFT)
+#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
#define I40E_IEEE_ETS_PRIO_0_SHIFT 0
#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
#define I40E_IEEE_ETS_PRIO_1_SHIFT 4
@@ -97,9 +97,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I40E_IEEE_PFC_CAP_SHIFT 0
#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
#define I40E_IEEE_PFC_MBC_SHIFT 6
-#define I40E_IEEE_PFC_MBC_MASK (0x1 << I40E_IEEE_PFC_MBC_SHIFT)
+#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
#define I40E_IEEE_PFC_WILLING_SHIFT 7
-#define I40E_IEEE_PFC_WILLING_MASK (0x1 << I40E_IEEE_PFC_WILLING_SHIFT)
+#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
/* Defines for IEEE APP TLV */
#define I40E_IEEE_APP_SEL_SHIFT 0
diff --git a/drivers/net/i40e/base/i40e_diag.c b/drivers/net/i40e/base/i40e_diag.c
index 55787c7..c3c76a0 100644
--- a/drivers/net/i40e/base/i40e_diag.c
+++ b/drivers/net/i40e/base/i40e_diag.c
@@ -156,13 +156,10 @@ enum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw)
ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val);
if ((ret_code == I40E_SUCCESS) &&
((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
- (0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {
- ret_code = i40e_validate_nvm_checksum(hw, NULL);
- } else {
- ret_code = I40E_ERR_DIAG_TEST_FAILED;
- }
-
- return ret_code;
+ BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))
+ return i40e_validate_nvm_checksum(hw, NULL);
+ else
+ return I40E_ERR_DIAG_TEST_FAILED;
}
/**
diff --git a/drivers/net/i40e/base/i40e_hmc.h b/drivers/net/i40e/base/i40e_hmc.h
index 41507e0..c2cdc92 100644
--- a/drivers/net/i40e/base/i40e_hmc.h
+++ b/drivers/net/i40e/base/i40e_hmc.h
@@ -133,8 +133,8 @@ struct i40e_hmc_info {
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
- (1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
- val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
+ BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
+ val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
wr32((hw), I40E_PFHMC_SDCMD, val3); \
@@ -153,7 +153,7 @@ struct i40e_hmc_info {
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
- val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
+ val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
wr32((hw), I40E_PFHMC_SDCMD, val3); \
diff --git a/drivers/net/i40e/base/i40e_lan_hmc.c b/drivers/net/i40e/base/i40e_lan_hmc.c
index ac9d36a..1533a62 100644
--- a/drivers/net/i40e/base/i40e_lan_hmc.c
+++ b/drivers/net/i40e/base/i40e_lan_hmc.c
@@ -136,7 +136,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
obj->cnt = txq_num;
obj->base = 0;
size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
- obj->size = (u64)1 << size_exp;
+ obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (txq_num > obj->max_cnt) {
@@ -159,7 +159,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
- obj->size = (u64)1 << size_exp;
+ obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (rxq_num > obj->max_cnt) {
@@ -182,7 +182,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
- obj->size = (u64)1 << size_exp;
+ obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (fcoe_cntx_num > obj->max_cnt) {
@@ -205,7 +205,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);
obj->base = i40e_align_l2obj_base(obj->base);
size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
- obj->size = (u64)1 << size_exp;
+ obj->size = BIT_ULL(size_exp);
/* validate values requested by driver don't exceed HMC capacity */
if (fcoe_filt_num > obj->max_cnt) {
@@ -770,7 +770,7 @@ static void i40e_write_byte(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
- mask = ((u8)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
src_byte = *from;
src_byte &= mask;
@@ -811,7 +811,7 @@ static void i40e_write_word(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
- mask = ((u16)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
/* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines
@@ -861,7 +861,7 @@ static void i40e_write_dword(u8 *hmc_bits,
* to 5 bits so the shift will do nothing
*/
if (ce_info->width < 32)
- mask = ((u32)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
else
mask = ~(u32)0;
@@ -913,7 +913,7 @@ static void i40e_write_qword(u8 *hmc_bits,
* to 6 bits so the shift will do nothing
*/
if (ce_info->width < 64)
- mask = ((u64)1 << ce_info->width) - 1;
+ mask = BIT_ULL(ce_info->width) - 1;
else
mask = ~(u64)0;
@@ -955,7 +955,7 @@ static void i40e_read_byte(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
- mask = ((u8)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
/* shift to correct alignment */
mask <<= shift_width;
@@ -993,7 +993,7 @@ static void i40e_read_word(u8 *hmc_bits,
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
- mask = ((u16)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
/* shift to correct alignment */
mask <<= shift_width;
@@ -1043,7 +1043,7 @@ static void i40e_read_dword(u8 *hmc_bits,
* to 5 bits so the shift will do nothing
*/
if (ce_info->width < 32)
- mask = ((u32)1 << ce_info->width) - 1;
+ mask = BIT(ce_info->width) - 1;
else
mask = ~(u32)0;
@@ -1096,7 +1096,7 @@ static void i40e_read_qword(u8 *hmc_bits,
* to 6 bits so the shift will do nothing
*/
if (ce_info->width < 64)
- mask = ((u64)1 << ce_info->width) - 1;
+ mask = BIT_ULL(ce_info->width) - 1;
else
mask = ~(u64)0;
diff --git a/drivers/net/i40e/base/i40e_nvm.c b/drivers/net/i40e/base/i40e_nvm.c
index 14b4e84..1c93c56 100644
--- a/drivers/net/i40e/base/i40e_nvm.c
+++ b/drivers/net/i40e/base/i40e_nvm.c
@@ -71,7 +71,7 @@ enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
I40E_GLNVM_GENS_SR_SIZE_SHIFT);
/* Switching to words (sr_size contains power of 2KB) */
- nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
+ nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
/* Check if we are in the normal or blank NVM programming mode */
fla = rd32(hw, I40E_GLNVM_FLA);
@@ -232,8 +232,8 @@ enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
ret_code = i40e_poll_sr_srctl_done_bit(hw);
if (ret_code == I40E_SUCCESS) {
/* Write the address and start reading */
- sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
- (1 << I40E_GLNVM_SRCTL_START_SHIFT);
+ sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
+ BIT(I40E_GLNVM_SRCTL_START_SHIFT);
wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
/* Poll I40E_GLNVM_SRCTL until the done bit is set */
diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 4ea9c2d..ccd7992 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -49,6 +49,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
#define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
+#ifndef LINUX_MACROS
+#ifndef BIT
+#define BIT(a) (1UL << (a))
+#endif /* BIT */
+#ifndef BIT_ULL
+#define BIT_ULL(a) (1ULL << (a))
+#endif /* BIT_ULL */
+#endif /* LINUX_MACROS */
+
#ifndef I40E_MASK
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
@@ -695,7 +704,7 @@ enum i40e_rx_desc_status_bits {
};
#define I40E_RXD_QW1_STATUS_SHIFT 0
-#define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
+#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
I40E_RXD_QW1_STATUS_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
@@ -703,8 +712,7 @@ enum i40e_rx_desc_status_bits {
I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
-#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
- I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
+#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
#define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
@@ -850,8 +858,7 @@ enum i40e_rx_ptype_payload_layer {
I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
-#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
- I40E_RXD_QW1_LENGTH_SPH_SHIFT)
+#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
#define I40E_RXD_QW1_NEXTP_SHIFT 38
#define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
@@ -1054,12 +1061,11 @@ enum i40e_tx_ctx_desc_eipt_offload {
#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
-#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
+#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
-#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
- I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
+#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
@@ -1164,8 +1170,7 @@ enum i40e_filter_program_desc_pcmd {
#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
-#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
- I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
+#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
I40E_TXD_FLTR_QW1_CMD_SHIFT)
--
2.4.0
next prev parent reply other threads:[~2015-09-06 7:12 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-06 7:11 [dpdk-dev] [PATCH 00/52] update i40e base driver Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 01/52] i40e/base: split device ids into a separate file Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 02/52] i40e/base: Add new device id for 20Gb and Fort pond device Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 03/52] i40e/base: add error status value decoding Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 04/52] i40e/base: Replace sprintf with i40e_debug Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 05/52] i40e/base: Merge Fortville SW 4 admin Q command header Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 06/52] i40e/base: Add module_types and update_link_info Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 07/52] i40e/base: grab the AQ spinlocks before clearing registers Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 08/52] i40e/base: add handling of writeback descriptor Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 09/52] i40e/base: Add info to nvm info struct for OEM version data Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 10/52] i40e/base: add wait states to NVM state machine Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 11/52] i40e/base: add commands to nvmupdate utility Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 12/52] i40e/base: Add promiscuous on VLAN support Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 13/52] i40e/base: Add a workaround to drop all flow control frames Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 14/52] i40e/base: Add Debug Dump Internal Data AQ command Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 15/52] i40e/base: OEM Post Update AQ command implementation Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 16/52] i40e/base: add VF capabilities to virtual channel interface Jingjing Wu
2015-09-06 7:11 ` Jingjing Wu [this message]
2015-09-06 7:11 ` [dpdk-dev] [PATCH 18/52] i40e/base: Add parsing for CEE DCBX TLVs Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 19/52] i40e/base: Prepare the local LLDP MIB in IEEE TLV Format Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 20/52] i40e/base: Refactor PHY structure and add phy_capabilities enum Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 21/52] i40e/base: Store CEE DCBX cfg from firmware and Cache the CEE TLV status Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 22/52] i40e/base: Add some more stats for FD SB and ATR status Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 23/52] i40e/base: Update Flex-10 related device/function capabilities Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 24/52] i40e/base: Wrap the register definitions for PF and VF driver Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 25/52] i40e/base: fix up type clash in i40e_aq_rc_to_posix conversion Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 26/52] i40e/base: Add new link status defines Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 27/52] i40e/base: fixup padding issue in get_cee_dcb_cfg_v1_resp Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 28/52] i40e/base: Add Tx Scheduling related AQ commands Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 29/52] i40e/base: Additional checks for CEE APP priority validity Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 30/52] i40e/base: Add support for pre-allocated pages for pd Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 31/52] i40e/base: clean up unneeded gotos Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 32/52] i40e/base: Handle admin Q timeout when releasing NVM Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 33/52] i40e/base: Add definition of GLINT_CTL register Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 34/52] i40e/base: Add virtchnl op for additional solaris config Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 35/52] i40e/base: drop func from debug print Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 36/52] i40e/base: add new X722 device Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 37/52] i40e/base: Add AQ functions to handle RSS Key and LUT programming Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 38/52] i40e/base: add proxy config admin q functions Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 39/52] i40e/base: add wol config admin queue functions Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 40/52] i40e/base: add WR_CSR_PROT wol/proxy capability parsing Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 41/52] i40e/base: FortPark has additional PCTYPES supported for RSS Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 42/52] i40e/base: FortPark changes to Rx and Tx descriptor for Outer UDP checksum offloads Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 43/52] i40e/base: use INLINE macro for better cross-platform code management Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 44/52] i40e/base: ESS Support Jingjing Wu
2015-09-06 7:11 ` [dpdk-dev] [PATCH 45/52] i40e/base: print FCoE capability reported by the device function Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 46/52] i40e/base: remove useless assignments Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 47/52] i40e/base: Increase pf reset max loop limit Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 48/52] i40e/base: Add FortPark specific registers Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 49/52] i40e/base: Allow for per-device FW API version Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 50/52] i40e/base: Add ATR command bit definition for FortPark Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 51/52] i40e/base: Explicitly assign enum index for VSI type Jingjing Wu
2015-09-06 7:12 ` [dpdk-dev] [PATCH 52/52] eal/common: add new i40e device id Jingjing Wu
2015-09-09 1:53 ` [dpdk-dev] [PATCH 00/52] update i40e base driver Zhang, Helin
2015-10-01 23:38 ` Thomas Monjalon
2015-10-02 8:24 ` Mcnamara, John
2015-10-08 2:46 ` Wu, Jingjing
2015-09-16 7:45 ` Xu, HuilongX
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