From: "Sekhar, Ashwin" <Ashwin.Sekhar@cavium.com>
To: "Jacob, Jerin" <Jerin.JacobKollanukkaran@cavium.com>
Cc: "john.mcnamara@intel.com" <john.mcnamara@intel.com>,
"halayli@gmail.com" <halayli@gmail.com>,
"jianbo.liu@linaro.org" <jianbo.liu@linaro.org>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add arm64 support
Date: Thu, 18 May 2017 09:00:41 +0000 [thread overview]
Message-ID: <1495098040.3692.3.camel@caviumnetworks.com> (raw)
In-Reply-To: <20170518085504.GA13709@jerin>
On Thu, 2017-05-18 at 14:25 +0530, Jerin Jacob wrote:
> -----Original Message-----
> >
> > Date: Thu, 18 May 2017 00:34:26 -0700
> > From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> > To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
> > jianbo.liu@linaro.org
> > Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.c
> > om>
> > Subject: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add
> > arm64
> > support
> > X-Mailer: git-send-email 2.12.2
> >
> > Updated Makefile to allow compilation for arm64 architecture.
> >
> > Added necessary arm64 support for lthread.
> >
> > Fixed minor compilation errors for arm64 compilation.
> >
> > Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
> > and x86_64.
> >
> > +void
> > +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx
> > __rte_unused)
> > +{
> > + /* SAVE CURRENT CONTEXT */
> > + asm volatile (
> > + /* Save SP */
> > + "mov x3, sp\n"
> > + "str x3, [x1, #0]\n"
> > +
> > + /* Save FP and LR */
> > + "stp x29, x30, [x1, #8]\n"
> > +
> > + /* Save Callee Saved Regs x19 - x28 */
> > + "stp x19, x20, [x1, #24]\n"
> > + "stp x21, x22, [x1, #40]\n"
> > + "stp x23, x24, [x1, #56]\n"
> > + "stp x25, x26, [x1, #72]\n"
> > + "stp x27, x28, [x1, #88]\n"
> > + );
> IMO, We need to save SIMD registers in the context as well.
> x86 code also not doing that, looks like it is an obvious bug in x86
> code as
> well.
>
Yes. You are correct. Need to save the bottom 64-bits of called saved
ASIMD regs v8-v15. Will update the patch.
next prev parent reply other threads:[~2017-05-18 9:02 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-17 18:19 [dpdk-dev] [PATCH] " Ashwin Sekhar T K
2017-05-17 18:44 ` Jerin Jacob
2017-05-18 6:35 ` Jianbo Liu
2017-05-18 7:38 ` Sekhar, Ashwin
2017-05-18 7:34 ` [dpdk-dev] [PATCH v2 0/2] " Ashwin Sekhar T K
2017-05-18 7:34 ` [dpdk-dev] [PATCH v2 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 7:34 ` [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-18 8:55 ` Jerin Jacob
2017-05-18 9:00 ` Sekhar, Ashwin [this message]
2017-05-18 10:21 ` [dpdk-dev] [PATCH v3 0/2] " Ashwin Sekhar T K
2017-05-18 10:21 ` [dpdk-dev] [PATCH v3 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 10:21 ` [dpdk-dev] [PATCH v3 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-03 20:57 ` Thomas Monjalon
2017-07-03 21:21 ` O'Driscoll, Tim
2017-07-04 7:37 ` Sekhar, Ashwin
2017-07-04 14:02 ` O'Driscoll, Tim
2017-07-04 8:05 ` [dpdk-dev] [PATCH v4 0/2] " Ashwin Sekhar T K
2017-07-04 8:05 ` [dpdk-dev] [PATCH v4 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:05 ` [dpdk-dev] [PATCH v4 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 8:22 ` [dpdk-dev] [PATCH v5 0/2] " Ashwin Sekhar T K
2017-07-04 8:22 ` [dpdk-dev] [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:22 ` [dpdk-dev] [PATCH v5 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 13:20 ` [dpdk-dev] [PATCH v5 0/2] " Thomas Monjalon
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