From: Rosen Xu <rosen.xu@intel.com>
To: dev@dpdk.org
Cc: declan.doherty@intel.com, shreyansh.jain@nxp.com,
tianfei.zhang@intel.com, hao.wu@intel.com,
gaetan.rivet@6wind.com
Subject: [dpdk-dev] [RFC 1/5] Add Intel FPGA BUS Command Parse Code
Date: Fri, 9 Mar 2018 23:39:00 +0800 [thread overview]
Message-ID: <1520609944-120305-2-git-send-email-rosen.xu@intel.com> (raw)
In-Reply-To: <1520609944-120305-1-git-send-email-rosen.xu@intel.com>
Signed-off-by: Rosen Xu <rosen.xu@intel.com>
---
lib/librte_eal/common/eal_common_options.c | 8 +++++++-
lib/librte_eal/common/eal_options.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
index 9f2f8d2..4fe0875 100644
--- a/lib/librte_eal/common/eal_common_options.c
+++ b/lib/librte_eal/common/eal_common_options.c
@@ -73,6 +73,7 @@
{OPT_VDEV, 1, NULL, OPT_VDEV_NUM },
{OPT_VFIO_INTR, 1, NULL, OPT_VFIO_INTR_NUM },
{OPT_VMWARE_TSC_MAP, 0, NULL, OPT_VMWARE_TSC_MAP_NUM },
+ {OPT_IFPGA, 1, NULL, OPT_IFPGA_NUM },
{0, 0, NULL, 0 }
};
@@ -1160,7 +1161,12 @@ static int xdigit2val(unsigned char c)
core_parsed = LCORE_OPT_MAP;
break;
-
+ case OPT_IFPGA_NUM:
+ if (eal_option_device_add(RTE_DEVTYPE_VIRTUAL,
+ optarg) < 0) {
+ return -1;
+ }
+ break;
/* don't know what to do, leave this to caller */
default:
return 1;
diff --git a/lib/librte_eal/common/eal_options.h b/lib/librte_eal/common/eal_options.h
index e86c711..bdbb2c4 100644
--- a/lib/librte_eal/common/eal_options.h
+++ b/lib/librte_eal/common/eal_options.h
@@ -55,6 +55,8 @@ enum {
OPT_VFIO_INTR_NUM,
#define OPT_VMWARE_TSC_MAP "vmware-tsc-map"
OPT_VMWARE_TSC_MAP_NUM,
+#define OPT_IFPGA "ifpga"
+ OPT_IFPGA_NUM,
OPT_LONG_MAX_NUM
};
--
1.8.3.1
next prev parent reply other threads:[~2018-03-09 15:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-09 15:38 [dpdk-dev] [RFC 0/5] Intel FPGA BUS Rosen Xu
2018-03-09 15:39 ` Rosen Xu [this message]
2018-03-09 15:39 ` [dpdk-dev] [RFC 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 5/5] Add Intel OPAE Share Code Rosen Xu
2018-04-04 9:51 ` [dpdk-dev] [RFC 0/5] Intel FPGA BUS Bruce Richardson
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