From: "Wei Hu (Xavier)" <xavier.huwei@huawei.com>
To: <dev@dpdk.org>
Cc: <xavier.huwei@huawei.com>
Subject: [dpdk-dev] [PATCH] lib/librte_eal: support SVE flag on ARM64
Date: Fri, 17 Jul 2020 20:08:29 +0800 [thread overview]
Message-ID: <1594987709-11768-1-git-send-email-xavier.huwei@huawei.com> (raw)
From: Chengwen Feng <fengchengwen@huawei.com>
SVE is the next-generation SIMD extension of the ARMv8-A AArch64
instruction set.
The related marco definition can be found in linux kernel:
arch/arm64/include/uapi/asm/hwcap.h
This patch supports getting cpu SVE feature on ARM64 platform.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
---
lib/librte_eal/arm/include/rte_cpuflags_64.h | 1 +
lib/librte_eal/arm/rte_cpuflags.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h b/lib/librte_eal/arm/include/rte_cpuflags_64.h
index 95cc014..069844d 100644
--- a/lib/librte_eal/arm/include/rte_cpuflags_64.h
+++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h
@@ -22,6 +22,7 @@ enum rte_cpu_flag_t {
RTE_CPUFLAG_SHA2,
RTE_CPUFLAG_CRC32,
RTE_CPUFLAG_ATOMICS,
+ RTE_CPUFLAG_SVE,
RTE_CPUFLAG_AARCH64,
/* The last item */
RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c
index caf3dc8..b1e220b 100644
--- a/lib/librte_eal/arm/rte_cpuflags.c
+++ b/lib/librte_eal/arm/rte_cpuflags.c
@@ -95,6 +95,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
FEAT_DEF(SHA2, REG_HWCAP, 6)
FEAT_DEF(CRC32, REG_HWCAP, 7)
FEAT_DEF(ATOMICS, REG_HWCAP, 8)
+ FEAT_DEF(SVE, REG_HWCAP, 22)
FEAT_DEF(AARCH64, REG_PLATFORM, 1)
};
#endif /* RTE_ARCH */
--
2.7.4
next reply other threads:[~2020-07-17 12:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 12:08 Wei Hu (Xavier) [this message]
2020-07-17 23:04 ` Honnappa Nagarahalli
2020-07-18 2:17 ` Wei Hu (Xavier)
2020-07-22 6:35 ` Ruifeng Wang
2020-08-17 12:43 ` Wei Hu (Xavier)
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