From: Anoob Joseph <anoobj@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>
Cc: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>,
Jerin Jacob <jerinj@marvell.com>,
Ankur Dwivedi <adwivedi@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>,
Anoob Joseph <anoobj@marvell.com>
Subject: [dpdk-dev] [PATCH v2 15/17] common/cnxk: add EC grp static vectors
Date: Fri, 25 Jun 2021 11:06:47 +0530 [thread overview]
Message-ID: <1624599410-29689-16-git-send-email-anoobj@marvell.com> (raw)
In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com>
From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
EC group static vectors are required for CPT asymmetric operations.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_ae.c | 142 ++++++++++++++++++++++++++++++++++++++++
drivers/common/cnxk/roc_ae.h | 7 ++
drivers/common/cnxk/version.map | 2 +
4 files changed, 152 insertions(+)
create mode 100644 drivers/common/cnxk/roc_ae.c
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 181b58e..4c5d318 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
deps = ['eal', 'pci', 'bus_pci', 'mbuf']
sources = files(
+ 'roc_ae.c',
'roc_ae_fpm_tables.c',
'roc_cpt.c',
'roc_cpt_debug.c',
diff --git a/drivers/common/cnxk/roc_ae.c b/drivers/common/cnxk/roc_ae.c
new file mode 100644
index 0000000..cf3f7fc
--- /dev/null
+++ b/drivers/common/cnxk/roc_ae.c
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+#define AE_EC_GRP_TBL_NAME "ae_ec_grp_tbl"
+
+struct ae_ec_grp_tbl {
+ uint64_t refcount;
+ uint8_t ec_grp_tbl[];
+};
+
+const struct roc_ae_ec_group ae_ec_grp[ROC_AE_EC_ID_PMAX] = {
+ {
+ .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
+ .length = 24},
+ .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0x99, 0xDE, 0xF8, 0x36, 0x14, 0x6B,
+ 0xC9, 0xB1, 0xB4, 0xD2, 0x28, 0x31},
+ .length = 24},
+ },
+ {
+ .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
+ .length = 28},
+ .order = {.data = {0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF,
+ 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF,
+ 0X16, 0XA2, 0XE0, 0XB8, 0XF0, 0X3E, 0X13,
+ 0XDD, 0X29, 0X45, 0X5C, 0X5C, 0X2A, 0X3D},
+ .length = 28},
+ },
+ {
+ .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF},
+ .length = 32},
+ .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xBC, 0xE6, 0xFA, 0xAD, 0xA7,
+ 0x17, 0x9E, 0x84, 0xF3, 0xB9, 0xCA, 0xC2,
+ 0xFC, 0x63, 0x25, 0x51},
+ .length = 32},
+ },
+ {.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF},
+ .length = 48},
+ .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xC7, 0x63, 0x4D, 0x81, 0xF4, 0x37, 0x2D, 0xDF,
+ 0x58, 0x1A, 0x0D, 0xB2, 0x48, 0xB0, 0xA7, 0x7A,
+ 0xEC, 0xEC, 0x19, 0x6A, 0xCC, 0xC5, 0x29, 0x73},
+ .length = 48}},
+ {.prime = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF},
+ .length = 66},
+ .order = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFA, 0x51, 0x86, 0x87, 0x83, 0xBF, 0x2F,
+ 0x96, 0x6B, 0x7F, 0xCC, 0x01, 0x48, 0xF7, 0x09,
+ 0xA5, 0xD0, 0x3B, 0xB5, 0xC9, 0xB8, 0x89, 0x9C,
+ 0x47, 0xAE, 0xBB, 0x6F, 0xB7, 0x1E, 0x91, 0x38,
+ 0x64, 0x09},
+ .length = 66}}};
+
+int
+roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl)
+{
+ const char name[] = AE_EC_GRP_TBL_NAME;
+ struct ae_ec_grp_tbl *ec_grp;
+ const struct plt_memzone *mz;
+ int i, len = 0;
+ uint8_t *data;
+
+ if (tbl == NULL)
+ return -EINVAL;
+
+ len = sizeof(ae_ec_grp);
+
+ mz = plt_memzone_lookup(name);
+ if (mz == NULL) {
+ /* Create memzone first time */
+ mz = plt_memzone_reserve_cache_align(
+ name, len + sizeof(struct ae_ec_grp_tbl));
+ if (mz == NULL)
+ return -ENOMEM;
+ }
+
+ ec_grp = mz->addr;
+
+ if (__atomic_fetch_add(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) != 0)
+ return 0;
+
+ data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t));
+
+ for (i = 0; i < ROC_AE_EC_ID_PMAX; i++) {
+ memcpy(data, &ae_ec_grp[i], sizeof(struct roc_ae_ec_group));
+ tbl[i] = (struct roc_ae_ec_group *)data;
+ data += sizeof(struct roc_ae_ec_group);
+ }
+
+ return 0;
+}
+
+void
+roc_ae_ec_grp_put(void)
+{
+ const char name[] = AE_EC_GRP_TBL_NAME;
+ const struct plt_memzone *mz;
+ struct ae_ec_grp_tbl *ec_grp;
+
+ mz = plt_memzone_lookup(name);
+ if (mz == NULL)
+ return;
+
+ ec_grp = mz->addr;
+ /* Decrement number of devices using EC grp table */
+ if (__atomic_sub_fetch(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) == 0)
+ plt_memzone_free(mz);
+}
diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h
index c549e18..5072cc5 100644
--- a/drivers/common/cnxk/roc_ae.h
+++ b/drivers/common/cnxk/roc_ae.h
@@ -53,4 +53,11 @@ struct roc_ae_ec_ctx {
uint8_t curveid;
};
+/* Buffer pointer */
+struct roc_ae_buf_ptr {
+ void *vaddr;
+};
+
+int __roc_api roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl);
+void __roc_api roc_ae_ec_grp_put(void);
#endif /* __ROC_AE_H__ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7a3b4a6..9611217 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -10,6 +10,8 @@ INTERNAL {
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
+ roc_ae_ec_grp_get;
+ roc_ae_ec_grp_put;
roc_ae_fpm_get;
roc_ae_fpm_put;
roc_clk_freq_get;
--
2.7.4
next prev parent reply other threads:[~2021-06-25 5:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 01/17] common/cnxk: add CPT HW defines Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 02/17] common/cnxk: update Rx inline IPsec mbox message format Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 03/17] common/cnxk: add CPT dev config routines Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 04/17] common/cnxk: add idev CPT set - get Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 05/17] common/cnxk: add mbox to configure RXC Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 06/17] common/cnxk: add CPT LF config Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 07/17] common/cnxk: add CPT diagnostics Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 08/17] common/cnxk: add CPT LF flush Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 09/17] common/cnxk: add inline IPsec configuration mbox Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 10/17] common/cnxk: add SE microcode defines Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 11/17] common/cnxk: add IE " Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 12/17] common/cnxk: add AE " Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 13/17] common/cnxk: add lmtline init Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 14/17] common/cnxk: add fpm tables Anoob Joseph
2021-06-25 5:36 ` Anoob Joseph [this message]
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 16/17] common/cnxk: add IPsec common code Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 17/17] common/cnxk: add SE set key functions in roc Anoob Joseph
2021-06-28 8:56 ` [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver Akhil Goyal
2021-06-28 9:06 ` Akhil Goyal
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