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From: Tyler Retzlaff <roretzla@linux.microsoft.com>
To: dev@dpdk.org
Cc: "Mattias Rönnblom" <mattias.ronnblom@ericsson.com>,
	"Min Hu (Connor)" <humin29@huawei.com>,
	"Morten Brørup" <mb@smartsharesystems.com>,
	"Abdullah Sevincer" <abdullah.sevincer@intel.com>,
	"Ajit Khaparde" <ajit.khaparde@broadcom.com>,
	"Akhil Goyal" <gakhil@marvell.com>,
	"Alok Prasad" <palok@marvell.com>,
	"Amit Bernstein" <amitbern@amazon.com>,
	"Anatoly Burakov" <anatoly.burakov@intel.com>,
	"Andrew Boyer" <andrew.boyer@amd.com>,
	"Andrew Rybchenko" <andrew.rybchenko@oktetlabs.ru>,
	"Ankur Dwivedi" <adwivedi@marvell.com>,
	"Anoob Joseph" <anoobj@marvell.com>,
	"Ashish Gupta" <ashish.gupta@marvell.com>,
	"Ashwin Sekhar T K" <asekhar@marvell.com>,
	"Bruce Richardson" <bruce.richardson@intel.com>,
	"Byron Marohn" <byron.marohn@intel.com>,
	"Chaoyong He" <chaoyong.he@corigine.com>,
	"Chas Williams" <chas3@att.com>,
	"Chenbo Xia" <chenbox@nvidia.com>,
	"Chengwen Feng" <fengchengwen@huawei.com>,
	"Conor Walsh" <conor.walsh@intel.com>,
	"Cristian Dumitrescu" <cristian.dumitrescu@intel.com>,
	"Dariusz Sosnowski" <dsosnowski@nvidia.com>,
	"David Hunt" <david.hunt@intel.com>,
	"Devendra Singh Rawat" <dsinghrawat@marvell.com>,
	"Ed Czeck" <ed.czeck@atomicrules.com>,
	"Evgeny Schemeilin" <evgenys@amazon.com>,
	"Fan Zhang" <fanzhang.oss@gmail.com>,
	"Gagandeep Singh" <g.singh@nxp.com>,
	"Guoyang Zhou" <zhouguoyang@huawei.com>,
	"Harman Kalra" <hkalra@marvell.com>,
	"Harry van Haaren" <harry.van.haaren@intel.com>,
	"Hemant Agrawal" <hemant.agrawal@nxp.com>,
	"Honnappa Nagarahalli" <honnappa.nagarahalli@arm.com>,
	"Hyong Youb Kim" <hyonkim@cisco.com>,
	"Jakub Grajciar" <jgrajcia@cisco.com>,
	"Jerin Jacob" <jerinj@marvell.com>,
	"Jian Wang" <jianwang@trustnetic.com>,
	"Jiawen Wu" <jiawenwu@trustnetic.com>,
	"Jie Hai" <haijie1@huawei.com>,
	"Jingjing Wu" <jingjing.wu@intel.com>,
	"John Daley" <johndale@cisco.com>,
	"John Miller" <john.miller@atomicrules.com>,
	"Joyce Kong" <joyce.kong@arm.com>, "Kai Ji" <kai.ji@intel.com>,
	"Kevin Laatz" <kevin.laatz@intel.com>,
	"Kiran Kumar K" <kirankumark@marvell.com>,
	"Konstantin Ananyev" <konstantin.v.ananyev@yandex.ru>,
	"Lee Daly" <lee.daly@intel.com>,
	"Liang Ma" <liangma@liangbit.com>,
	"Liron Himi" <lironh@marvell.com>,
	"Long Li" <longli@microsoft.com>,
	"Maciej Czekaj" <mczekaj@marvell.com>,
	"Matan Azrad" <matan@nvidia.com>,
	"Matt Peters" <matt.peters@windriver.com>,
	"Maxime Coquelin" <maxime.coquelin@redhat.com>,
	"Michael Shamis" <michaelsh@marvell.com>,
	"Nagadheeraj Rottela" <rnagadheeraj@marvell.com>,
	"Nicolas Chautru" <nicolas.chautru@intel.com>,
	"Nithin Dabilpuram" <ndabilpuram@marvell.com>,
	"Ori Kam" <orika@nvidia.com>,
	"Pablo de Lara" <pablo.de.lara.guarch@intel.com>,
	"Pavan Nikhilesh" <pbhagavatula@marvell.com>,
	"Peter Mccarthy" <peter.mccarthy@intel.com>,
	"Radu Nicolau" <radu.nicolau@intel.com>,
	"Rahul Lakkireddy" <rahul.lakkireddy@chelsio.com>,
	"Rakesh Kudurumalla" <rkudurumalla@marvell.com>,
	"Raveendra Padasalagi" <raveendra.padasalagi@broadcom.com>,
	"Reshma Pattan" <reshma.pattan@intel.com>,
	"Ron Beider" <rbeider@amazon.com>,
	"Ruifeng Wang" <ruifeng.wang@arm.com>,
	"Sachin Saxena" <sachin.saxena@nxp.com>,
	"Selwin Sebastian" <selwin.sebastian@amd.com>,
	"Shai Brandes" <shaibran@amazon.com>,
	"Shepard Siegel" <shepard.siegel@atomicrules.com>,
	"Shijith Thotton" <sthotton@marvell.com>,
	"Sivaprasad Tummala" <sivaprasad.tummala@amd.com>,
	"Somnath Kotur" <somnath.kotur@broadcom.com>,
	"Srikanth Yalavarthi" <syalavarthi@marvell.com>,
	"Stephen Hemminger" <stephen@networkplumber.org>,
	"Steven Webster" <steven.webster@windriver.com>,
	"Suanming Mou" <suanmingm@nvidia.com>,
	"Sunil Kumar Kori" <skori@marvell.com>,
	"Sunil Uttarwar" <sunilprakashrao.uttarwar@amd.com>,
	"Sunila Sahu" <ssahu@marvell.com>,
	"Tejasree Kondoj" <ktejasree@marvell.com>,
	"Viacheslav Ovsiienko" <viacheslavo@nvidia.com>,
	"Vikas Gupta" <vikas.gupta@broadcom.com>,
	"Volodymyr Fialko" <vfialko@marvell.com>,
	"Wajeeh Atrash" <atrwajee@amazon.com>,
	"Wisam Jaddo" <wisamm@nvidia.com>,
	"Xiaoyun Wang" <cloud.wangxiaoyun@huawei.com>,
	"Yipeng Wang" <yipeng1.wang@intel.com>,
	"Yisen Zhuang" <yisen.zhuang@huawei.com>,
	"Yuying Zhang" <Yuying.Zhang@intel.com>,
	"Zhangfei Gao" <zhangfei.gao@linaro.org>,
	"Zhirun Yan" <yanzhirun_163@163.com>,
	"Ziyang Xuan" <xuanziyang2@huawei.com>,
	"Tyler Retzlaff" <roretzla@linux.microsoft.com>
Subject: [PATCH v2 21/83] net/mlx5: move alignment attribute on types
Date: Mon, 15 Apr 2024 13:03:43 -0700	[thread overview]
Message-ID: <1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com> (raw)
In-Reply-To: <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>

Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
---
 drivers/net/mlx5/hws/mlx5dr_send.h |  4 ++--
 drivers/net/mlx5/mlx5.h            |  6 +++---
 drivers/net/mlx5/mlx5_flow.h       |  4 ++--
 drivers/net/mlx5/mlx5_hws_cnt.h    | 14 +++++++-------
 drivers/net/mlx5/mlx5_rx.h         |  4 ++--
 drivers/net/mlx5/mlx5_rxtx.c       |  6 +++---
 drivers/net/mlx5/mlx5_tx.h         | 10 +++++-----
 drivers/net/mlx5/mlx5_utils.h      |  2 +-
 8 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h
index c4eaea5..0c67a9e 100644
--- a/drivers/net/mlx5/hws/mlx5dr_send.h
+++ b/drivers/net/mlx5/hws/mlx5dr_send.h
@@ -144,7 +144,7 @@ struct mlx5dr_completed_poll {
 	uint16_t mask;
 };
 
-struct mlx5dr_send_engine {
+struct __rte_cache_aligned mlx5dr_send_engine {
 	struct mlx5dr_send_ring send_ring[MLX5DR_NUM_SEND_RINGS]; /* For now 1:1 mapping */
 	struct mlx5dv_devx_uar *uar; /* Uar is shared between rings of a queue */
 	struct mlx5dr_completed_poll completed;
@@ -153,7 +153,7 @@ struct mlx5dr_send_engine {
 	uint16_t rings;
 	uint16_t num_entries;
 	bool err;
-} __rte_cache_aligned;
+};
 
 struct mlx5dr_send_engine_post_ctrl {
 	struct mlx5dr_send_engine *queue;
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 0091a24..3646d20 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -415,7 +415,7 @@ struct mlx5_hw_q_job {
 };
 
 /* HW steering job descriptor LIFO pool. */
-struct mlx5_hw_q {
+struct __rte_cache_aligned mlx5_hw_q {
 	uint32_t job_idx; /* Free job index. */
 	uint32_t size; /* Job LIFO queue size. */
 	uint32_t ongoing_flow_ops; /* Number of ongoing flow operations. */
@@ -424,7 +424,7 @@ struct mlx5_hw_q {
 	struct rte_ring *indir_iq; /* Indirect action SW in progress queue. */
 	struct rte_ring *flow_transfer_pending;
 	struct rte_ring *flow_transfer_completed;
-} __rte_cache_aligned;
+};
 
 
 #define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15)
@@ -1405,7 +1405,7 @@ struct mlx5_hws_cnt_svc_mng {
 	uint32_t query_interval;
 	rte_thread_t service_thread;
 	uint8_t svc_running;
-	struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_aso_mng aso_mng;
 };
 
 #define MLX5_FLOW_HW_TAGS_MAX 12
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 0065727..cc1e8cf 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1654,9 +1654,9 @@ struct mlx5_matcher_info {
 	RTE_ATOMIC(uint32_t) refcnt;
 };
 
-struct mlx5_dr_rule_action_container {
+struct __rte_cache_aligned mlx5_dr_rule_action_container {
 	struct mlx5dr_rule_action acts[MLX5_HW_MAX_ACTS];
-} __rte_cache_aligned;
+};
 
 struct rte_flow_template_table {
 	LIST_ENTRY(rte_flow_template_table) next;
diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h
index e005960..1cb0564 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.h
+++ b/drivers/net/mlx5/mlx5_hws_cnt.h
@@ -97,11 +97,11 @@ struct mlx5_hws_cnt_pool_caches {
 	struct rte_ring *qcache[];
 };
 
-struct mlx5_hws_cnt_pool {
+struct __rte_cache_aligned mlx5_hws_cnt_pool {
 	LIST_ENTRY(mlx5_hws_cnt_pool) next;
-	struct mlx5_hws_cnt_pool_cfg cfg __rte_cache_aligned;
-	struct mlx5_hws_cnt_dcs_mng dcs_mng __rte_cache_aligned;
-	uint32_t query_gen __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_cnt_pool_cfg cfg;
+	alignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_cnt_dcs_mng dcs_mng;
+	alignas(RTE_CACHE_LINE_SIZE) uint32_t query_gen;
 	struct mlx5_hws_cnt *pool;
 	struct mlx5_hws_cnt_raw_data_mng *raw_mng;
 	struct rte_ring *reuse_list;
@@ -110,7 +110,7 @@ struct mlx5_hws_cnt_pool {
 	struct mlx5_hws_cnt_pool_caches *cache;
 	uint64_t time_of_last_age_check;
 	struct mlx5_priv *priv;
-} __rte_cache_aligned;
+};
 
 /* HWS AGE status. */
 enum {
@@ -133,7 +133,7 @@ enum {
 };
 
 /* HWS counter age parameter. */
-struct mlx5_hws_age_param {
+struct __rte_cache_aligned mlx5_hws_age_param {
 	uint32_t timeout; /* Aging timeout in seconds (atomically accessed). */
 	uint32_t sec_since_last_hit;
 	/* Time in seconds since last hit (atomically accessed). */
@@ -149,7 +149,7 @@ struct mlx5_hws_age_param {
 	cnt_id_t own_cnt_index;
 	/* Counter action created specifically for this AGE action. */
 	void *context; /* Flow AGE context. */
-} __rte_packed __rte_cache_aligned;
+} __rte_packed;
 
 
 /**
diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h
index 2fce908..fb4d8e6 100644
--- a/drivers/net/mlx5/mlx5_rx.h
+++ b/drivers/net/mlx5/mlx5_rx.h
@@ -79,7 +79,7 @@ struct mlx5_eth_rxseg {
 };
 
 /* RX queue descriptor. */
-struct mlx5_rxq_data {
+struct __rte_cache_aligned mlx5_rxq_data {
 	unsigned int csum:1; /* Enable checksum offloading. */
 	unsigned int hw_timestamp:1; /* Enable HW timestamp. */
 	unsigned int rt_timestamp:1; /* Realtime timestamp format. */
@@ -146,7 +146,7 @@ struct mlx5_rxq_data {
 	uint32_t rxseg_n; /* Number of split segment descriptions. */
 	struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];
 	/* Buffer split segment descriptions - sizes, offsets, pools. */
-} __rte_cache_aligned;
+};
 
 /* RX queue control descriptor. */
 struct mlx5_rxq_ctrl {
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 54d410b..d3d4470 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -77,12 +77,12 @@
 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
 		"invalid WQE size");
 
-uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
+alignas(RTE_CACHE_LINE_SIZE) uint32_t mlx5_ptype_table[] = {
 	[0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
 };
 
-uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
-uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
+alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_cksum_table[1 << 10];
+alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_swp_types_table[1 << 10];
 
 uint64_t rte_net_mlx5_dynf_inline_mask;
 
diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index b1e8ea1..107d7ab 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -83,9 +83,9 @@ enum mlx5_txcmp_code {
 extern uint64_t rte_net_mlx5_dynf_inline_mask;
 #define RTE_MBUF_F_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
 
-extern uint32_t mlx5_ptype_table[] __rte_cache_aligned;
-extern uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
-extern uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
+extern alignas(RTE_CACHE_LINE_SIZE) uint32_t mlx5_ptype_table[];
+extern alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_cksum_table[1 << 10];
+extern alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_swp_types_table[1 << 10];
 
 struct mlx5_txq_stats {
 #ifdef MLX5_PMD_SOFT_COUNTERS
@@ -112,7 +112,7 @@ struct mlx5_txq_local {
 
 /* TX queue descriptor. */
 __extension__
-struct mlx5_txq_data {
+struct __rte_cache_aligned mlx5_txq_data {
 	uint16_t elts_head; /* Current counter in (*elts)[]. */
 	uint16_t elts_tail; /* Counter of first element awaiting completion. */
 	uint16_t elts_comp; /* elts index since last completion request. */
@@ -173,7 +173,7 @@ struct mlx5_txq_data {
 	struct mlx5_uar_data uar_data;
 	struct rte_mbuf *elts[];
 	/* Storage for queued packets, must be the last field. */
-} __rte_cache_aligned;
+};
 
 /* TX queue control descriptor. */
 __extension__
diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h
index f3c0d76..b51d977 100644
--- a/drivers/net/mlx5/mlx5_utils.h
+++ b/drivers/net/mlx5/mlx5_utils.h
@@ -235,7 +235,7 @@ struct mlx5_indexed_trunk {
 	uint32_t next; /* Next free trunk in free list. */
 	uint32_t free; /* Free entries available */
 	struct rte_bitmap *bmp;
-	uint8_t data[] __rte_cache_aligned; /* Entry data start. */
+	alignas(RTE_CACHE_LINE_SIZE) uint8_t data[]; /* Entry data start. */
 };
 
 struct mlx5_indexed_cache {
-- 
1.8.3.1


  parent reply	other threads:[~2024-04-15 20:07 UTC|newest]

Thread overview: 181+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-20 15:36 [PATCH 00/83] " Tyler Retzlaff
2024-03-20 15:36 ` [PATCH 01/83] examples: " Tyler Retzlaff
2024-04-06 14:55   ` Morten Brørup
2024-04-08 15:44     ` Tyler Retzlaff
2024-04-10 15:29     ` Akhil Goyal
2024-03-20 15:36 ` [PATCH 02/83] net/ark: " Tyler Retzlaff
2024-03-20 15:36 ` [PATCH 03/83] net/avp: " Tyler Retzlaff
2024-03-20 15:36 ` [PATCH 04/83] net/axgbe: " Tyler Retzlaff
2024-03-20 15:36 ` [PATCH 05/83] net/bnxt: " Tyler Retzlaff
2024-03-20 15:36 ` [PATCH 06/83] net/bonding: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 07/83] net/cxgbe: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 08/83] net/e1000: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 09/83] net/ena: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 10/83] net/enic: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 11/83] net/fm10k: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 12/83] net/hinic: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 13/83] net/hns3: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 14/83] net/i40e: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 15/83] net/iavf: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 16/83] net/ice: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 17/83] net/igc: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 18/83] net/ionic: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 19/83] net/ixgbe: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 20/83] net/memif: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 21/83] net/mlx5: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 22/83] net/mlx4: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 23/83] net/mvpp2: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 24/83] net/netvsc: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 25/83] net/nfp: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 26/83] net/ngbe: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 27/83] net/octeontx: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 28/83] net/pfe: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 29/83] net/qede: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 30/83] net/softnic: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 31/83] net/tap: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 32/83] net/thunderx: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 33/83] net/txgbe: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 34/83] net/virtio: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 35/83] vdpa/mlx5: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 36/83] regex/cn9k: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 37/83] raw/ntb: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 38/83] ml/cnxk: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 39/83] mempool/cnxk: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 40/83] event/sw: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 41/83] event/skeleton: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 42/83] event/opdl: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 43/83] event/octeontx: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 44/83] event/dsw: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 45/83] event/dlb2: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 46/83] event/cnxk: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 47/83] dma/skeleton: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 48/83] dma/ioat: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 49/83] dma/idxd: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 50/83] crypto/uadk: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 51/83] crypto/scheduler: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 52/83] crypto/qat: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 53/83] crypto/openssl: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 54/83] crypto/octeontx: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 55/83] crypto/null: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 56/83] crypto/mvsam: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 57/83] crypto/mlx5: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 58/83] crypto/ipsec_mb: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 59/83] crypto/cnxk: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 60/83] crypto/ccp: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 61/83] crypto/caam_jr: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 62/83] crypto/bcmfs: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 63/83] crypto/armv8: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 64/83] compress/zlib: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 65/83] compress/qat: " Tyler Retzlaff
2024-03-20 15:37 ` [PATCH 66/83] compress/octeontx: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 67/83] compress/nitrox: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 68/83] compress/isal: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 69/83] common/qat: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 70/83] common/mlx5: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 71/83] common/idpf: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 72/83] common/cpt: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 73/83] bus/fslmc: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 74/83] baseband/turbo_sw: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 75/83] baseband/null: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 76/83] app/test: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 77/83] app/test-pipeline: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 78/83] app/test-mldev: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 79/83] app/test-flow-perf: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 80/83] app/test-eventdev: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 81/83] app/pdump: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 82/83] app/graph: " Tyler Retzlaff
2024-03-20 15:38 ` [PATCH 83/83] bus/dpaa: " Tyler Retzlaff
2024-03-20 15:50 ` [PATCH 00/83] " Bruce Richardson
2024-03-20 16:00   ` David Marchand
2024-03-20 17:40   ` Morten Brørup
2024-03-20 17:41 ` David Marchand
2024-03-20 19:12   ` Tyler Retzlaff
2024-04-02 17:56 ` Tyler Retzlaff
2024-04-15 20:03 ` [PATCH v2 " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 01/83] examples: " Tyler Retzlaff
2024-04-17  6:21     ` [EXTERNAL] " Akhil Goyal
2024-04-15 20:03   ` [PATCH v2 02/83] net/ark: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 03/83] net/avp: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 04/83] net/axgbe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 05/83] net/bnxt: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 06/83] net/bonding: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 07/83] net/cxgbe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 08/83] net/e1000: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 09/83] net/ena: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 10/83] net/enic: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 11/83] net/fm10k: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 12/83] net/hinic: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 13/83] net/hns3: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 14/83] net/i40e: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 15/83] net/iavf: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 16/83] net/ice: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 17/83] net/igc: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 18/83] net/ionic: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 19/83] net/ixgbe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 20/83] net/memif: " Tyler Retzlaff
2024-04-15 20:03   ` Tyler Retzlaff [this message]
2024-04-15 20:03   ` [PATCH v2 22/83] net/mlx4: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 23/83] net/mvpp2: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 24/83] net/netvsc: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 25/83] net/nfp: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 26/83] net/ngbe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 27/83] net/octeontx: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 28/83] net/pfe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 29/83] net/qede: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 30/83] net/softnic: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 31/83] net/tap: " Tyler Retzlaff
2024-05-02 18:33     ` Stephen Hemminger
2024-04-15 20:03   ` [PATCH v2 32/83] net/thunderx: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 33/83] net/txgbe: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 34/83] net/virtio: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 35/83] vdpa/mlx5: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 36/83] regex/cn9k: " Tyler Retzlaff
2024-04-15 20:03   ` [PATCH v2 37/83] raw/ntb: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 38/83] ml/cnxk: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 39/83] mempool/cnxk: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 40/83] event/sw: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 41/83] event/skeleton: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 42/83] event/opdl: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 43/83] event/octeontx: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 44/83] event/dsw: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 45/83] event/dlb2: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 46/83] event/cnxk: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 47/83] dma/skeleton: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 48/83] dma/ioat: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 49/83] dma/idxd: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 50/83] crypto/uadk: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 51/83] crypto/scheduler: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 52/83] crypto/qat: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 53/83] crypto/openssl: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 54/83] crypto/octeontx: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 55/83] crypto/null: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 56/83] crypto/mvsam: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 57/83] crypto/mlx5: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 58/83] crypto/ipsec_mb: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 59/83] crypto/cnxk: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 60/83] crypto/ccp: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 61/83] crypto/caam_jr: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 62/83] crypto/bcmfs: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 63/83] crypto/armv8: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 64/83] compress/zlib: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 65/83] compress/qat: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 66/83] compress/octeontx: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 67/83] compress/nitrox: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 68/83] compress/isal: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 69/83] common/qat: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 70/83] common/mlx5: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 71/83] common/idpf: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 72/83] common/cpt: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 73/83] bus/fslmc: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 74/83] baseband/turbo_sw: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 75/83] baseband/null: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 76/83] app/test: " Tyler Retzlaff
2024-04-17  6:18     ` [EXTERNAL] " Akhil Goyal
2024-04-15 20:04   ` [PATCH v2 77/83] app/test-pipeline: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 78/83] app/test-mldev: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 79/83] app/test-flow-perf: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 80/83] app/test-eventdev: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 81/83] app/pdump: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 82/83] app/graph: " Tyler Retzlaff
2024-04-15 20:04   ` [PATCH v2 83/83] bus/dpaa: " Tyler Retzlaff
2024-04-19 15:05   ` [PATCH v2 00/83] " David Marchand

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