From: Ferruh Yigit <ferruh.yigit@intel.com>
To: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>,
ravi1.kumar@amd.com, thomas@monjalon.net
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
Date: Wed, 18 Apr 2018 18:44:12 +0100 [thread overview]
Message-ID: <1b2518da-f9ad-5ece-d72d-7af1a1c364e6@intel.com> (raw)
In-Reply-To: <7b899916-0949-f387-58df-d71541ac575f@intel.com>
On 4/18/2018 6:17 PM, Ferruh Yigit wrote:
> On 4/17/2018 9:04 PM, Pavan Nikhilesh wrote:
>> Due to missing ____cacheline_aligned definition compiler treats it as a
>> global variable replace it with proper cache alignment macro.
>>
>> Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
>>
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
>
> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Applied to dpdk-next-net/master, thanks.
next prev parent reply other threads:[~2018-04-18 17:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-17 20:04 Pavan Nikhilesh
2018-04-18 17:17 ` Ferruh Yigit
2018-04-18 17:44 ` Ferruh Yigit [this message]
2018-04-23 6:32 ` Kumar, Ravi1
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