From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
To: Stephen Hemminger <stephen@networkplumber.org>
Cc: Yerden Zhumabekov <e_zhumabekov@sts.kz>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"Verkamp, Daniel" <daniel.verkamp@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
Date: Fri, 9 Jun 2017 22:58:55 +0530 [thread overview]
Message-ID: <20170609172854.GA2828@jerin> (raw)
In-Reply-To: <20170609101625.09075858@xeon-e3>
-----Original Message-----
> Date: Fri, 9 Jun 2017 10:16:25 -0700
> From: Stephen Hemminger <stephen@networkplumber.org>
> To: Yerden Zhumabekov <e_zhumabekov@sts.kz>
> Cc: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>, "Richardson,
> Bruce" <bruce.richardson@intel.com>, "Verkamp, Daniel"
> <daniel.verkamp@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
> Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
>
> On Fri, 9 Jun 2017 18:47:43 +0600
> Yerden Zhumabekov <e_zhumabekov@sts.kz> wrote:
>
> > On 06.06.2017 19:19, Ananyev, Konstantin wrote:
> > >
> > >>>> Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h?
> > >>> Might be, would be good to hear opinion the author of that change.
> > >> It gives improved performance for core-2-core transfer.
> > > You mean empty cache-line(s) after prod/cons, correct?
> > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries?
> > > Something like that:
> > > struct rte_ring {
> > > ...
> > > struct rte_ring_headtail prod __rte_cache_aligned;
> > > EMPTY_CACHE_LINE __rte_cache_aligned;
> > > struct rte_ring_headtail cons __rte_cache_aligned;
> > > EMPTY_CACHE_LINE __rte_cache_aligned;
> > > };
> > >
> > > Konstantin
> > >
> >
> > I'm curious, can anyone explain, how does it actually affect
> > performance? Maybe we can utilize it application code?
>
> I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines.
> If these cache lines change, then it will create false sharing.
I see. I think, In such cases it is better to abstract as conditional
compilation. The above logic has worst case cache memory
requirement if CPU is 128B CL and no speculative prefetch.
next prev parent reply other threads:[~2017-06-09 17:29 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-02 20:03 [dpdk-dev] [PATCH] " Daniel Verkamp
2017-06-02 20:12 ` [dpdk-dev] [PATCH v2] " Daniel Verkamp
2017-06-02 20:51 ` Ananyev, Konstantin
2017-06-02 22:24 ` Verkamp, Daniel
2017-06-03 10:00 ` Ananyev, Konstantin
2017-06-05 16:21 ` Verkamp, Daniel
2017-06-06 9:59 ` Ananyev, Konstantin
2017-06-06 12:42 ` Bruce Richardson
2017-06-06 13:19 ` Ananyev, Konstantin
2017-06-06 14:56 ` Bruce Richardson
2017-06-08 12:45 ` Olivier Matz
2017-06-08 13:20 ` Bruce Richardson
2017-06-08 14:05 ` Olivier Matz
2017-06-08 14:11 ` Bruce Richardson
2017-06-08 14:50 ` Ananyev, Konstantin
2017-06-08 15:24 ` Bruce Richardson
2017-06-08 15:35 ` Ananyev, Konstantin
2017-06-08 16:03 ` Bruce Richardson
2017-06-08 16:12 ` Ananyev, Konstantin
2017-06-08 16:20 ` Richardson, Bruce
2017-06-08 16:42 ` Ananyev, Konstantin
2017-06-09 9:02 ` Bruce Richardson
2017-06-12 9:02 ` Olivier Matz
2017-06-12 9:56 ` Bruce Richardson
2017-06-30 11:35 ` Olivier Matz
2017-06-09 12:47 ` Yerden Zhumabekov
2017-06-09 17:16 ` Stephen Hemminger
2017-06-09 17:28 ` Jerin Jacob [this message]
2017-06-10 8:16 ` Ananyev, Konstantin
2017-06-12 3:07 ` Jerin Jacob
2017-06-12 10:18 ` Ananyev, Konstantin
2017-06-12 10:34 ` Jerin Jacob
2017-06-12 11:09 ` Bruce Richardson
2017-06-12 11:41 ` Jerin Jacob
2017-06-12 12:17 ` Ananyev, Konstantin
2017-06-12 12:42 ` Jerin Jacob
2017-06-12 12:51 ` Ananyev, Konstantin
2017-06-12 13:06 ` Bruce Richardson
2017-06-12 13:20 ` Jerin Jacob
2017-06-30 11:36 ` Olivier Matz
2017-07-01 11:14 ` Thomas Monjalon
2017-07-01 11:25 ` Thomas Monjalon
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