From: Bruce Richardson <bruce.richardson@intel.com>
To: Shahaf Shuler <shahafs@mellanox.com>
Cc: "Nélio Laranjeiro" <nelio.laranjeiro@6wind.com>,
"Sagi Grimberg" <sagi@grimberg.me>, "dev@dpdk.org" <dev@dpdk.org>,
"Adrien Mazarguil" <adrien.mazarguil@6wind.com>
Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type
Date: Thu, 24 Aug 2017 10:27:00 +0100 [thread overview]
Message-ID: <20170824092659.GA17904@bricha3-MOBL3.ger.corp.intel.com> (raw)
In-Reply-To: <VI1PR05MB3149CCD7C9A72D31AA6AA2D7C39A0@VI1PR05MB3149.eurprd05.prod.outlook.com>
On Thu, Aug 24, 2017 at 06:56:11AM +0000, Shahaf Shuler wrote:
> Wednesday, August 23, 2017 4:12 PM, Bruce Richardson:
> > On Wed, Aug 23, 2017 at 01:39:08PM +0200, Nélio Laranjeiro wrote:
> > > On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote:
> > >
> > > Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
> > >
> > While a compiler barrier may do on platforms with strong ordering, I'm
> > wondering if the rte_smp_wmb() macro may be needed here to give
> > compiler barrier or actual memory barrier depending on platform?
>
> Thanks for the catch!
>
> However, the description of rte_smp_wmb() not seems to fit our case here.
> We don't try to sync between different lcores, rather between the device and a single lcore.
>
> Maybe rte_io_wmb fits better?
>
Yep. Looks about right.
/Bruce
next prev parent reply other threads:[~2017-08-24 9:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-21 7:47 [dpdk-dev] [PATCH 0/2] mlx5 high latency observed on send operations Sagi Grimberg
2017-08-21 7:47 ` [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type Sagi Grimberg
2017-08-23 11:39 ` Nélio Laranjeiro
2017-08-23 13:11 ` Bruce Richardson
2017-08-24 6:56 ` Shahaf Shuler
2017-08-24 9:27 ` Bruce Richardson [this message]
2017-08-21 7:47 ` [dpdk-dev] [PATCH 2/2] net/mlx5: don't map doorbell register to write combining Sagi Grimberg
2017-08-23 11:03 ` Ferruh Yigit
2017-08-23 12:06 ` Nélio Laranjeiro
2017-08-27 6:47 ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Shahaf Shuler
2017-08-27 6:47 ` [dpdk-dev] [PATCH v2 1/2] net/mlx5: replace memory barrier type Shahaf Shuler
2017-08-27 6:47 ` [dpdk-dev] [PATCH v2 2/2] net/mlx5: don't map doorbell register to write combining Shahaf Shuler
2017-08-29 16:53 ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Ferruh Yigit
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