From: Olivier Matz <olivier.matz@6wind.com>
To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com
Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure
Date: Tue, 3 Apr 2018 17:25:17 +0200 [thread overview]
Message-ID: <20180403152517.hsjghkj5z6mauze7@platinum> (raw)
In-Reply-To: <20180403150722.GB15937@jerin>
On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote:
> -----Original Message-----
> > Date: Tue, 3 Apr 2018 15:26:44 +0200
> > From: Olivier Matz <olivier.matz@6wind.com>
> > To: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring
> > structure
> > X-Mailer: git-send-email 2.11.0
> >
> > The initial objective of
> > commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
> > was to add an empty cache line betwee, the producer and consumer
> > data (on platform with cache line size = 64B), preventing from
> > having them on adjacent cache lines.
> >
> > Following discussion on the mailing list, it appears that this
> > also imposes an alignment constraint that is not required.
> >
> > This patch removes the extra alignment constraint and adds the
> > empty cache lines using padding fields in the structure. The
> > size of rte_ring structure and the offset of the fields remain
> > the same on platforms with cache line size = 64B:
> >
> > rte_ring = 384
> > rte_ring.name = 0
> > rte_ring.flags = 32
> > rte_ring.memzone = 40
> > rte_ring.size = 48
> > rte_ring.mask = 52
> > rte_ring.prod = 128
> > rte_ring.cons = 256
> >
> > But it has an impact on platform where cache line size is 128B:
> >
> > rte_ring = 384 -> 768
> > rte_ring.name = 0
> > rte_ring.flags = 32
> > rte_ring.memzone = 40
> > rte_ring.size = 48
> > rte_ring.mask = 52
> > rte_ring.prod = 128 -> 256
> > rte_ring.cons = 256 -> 512
>
> Are we leaving TWO cacheline to make sure, HW prefetch don't load
> the adjust cacheline(consumer)?
>
> If so, Will it have impact on those machine where it is 128B Cache line
> and the HW prefetcher is not loading the next caching explicitly. Right?
The impact on machines that have a 128B cache line is that an unused
cache line will be added between the producer and consumer data. I
expect that the impact is positive in case there is a hw prefetcher, and
null in case there is no such prefetcher.
On machines with 64B cache line, this was already the case. It just
reduces the alignment constraint.
Olivier
next prev parent reply other threads:[~2018-04-03 15:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-30 14:26 [dpdk-dev] [RFC] " Olivier Matz
2017-07-20 8:52 ` Olivier Matz
2018-04-03 13:26 ` [dpdk-dev] [PATCH] " Olivier Matz
2018-04-03 15:07 ` Jerin Jacob
2018-04-03 15:25 ` Olivier Matz [this message]
2018-04-03 15:37 ` Jerin Jacob
2018-04-03 15:56 ` Olivier Matz
2018-04-03 16:42 ` Jerin Jacob
2018-04-04 23:38 ` Ananyev, Konstantin
2018-04-05 8:01 ` Jerin Jacob
2018-04-05 13:49 ` Ananyev, Konstantin
2018-04-06 1:26 ` Jerin Jacob
2018-04-11 0:33 ` Ananyev, Konstantin
2018-04-11 2:48 ` Jerin Jacob
2018-04-11 8:40 ` Ananyev, Konstantin
2018-04-17 22:15 ` Thomas Monjalon
2018-05-25 10:59 ` Burakov, Anatoly
2018-05-25 12:18 ` Burakov, Anatoly
2018-05-25 14:57 ` Burakov, Anatoly
2018-05-25 15:17 ` Olivier Matz
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