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From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: David Christensen <drc@linux.vnet.ibm.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on	power CPUs
Date: Tue, 7 May 2019 10:40:29 +0000	[thread overview]
Message-ID: <2601191342CEEE43887BDE71AB9772580148AA219D@irsmsx105.ger.corp.intel.com> (raw)
Message-ID: <20190507104029.L5HsHZo6I0Zbuux1KM936olOJxrLoIMFL5Nn75WSoTM@z> (raw)
In-Reply-To: <1557170647-99966-1-git-send-email-drc@linux.vnet.ibm.com>



> 
> The memory barrier test fails on IBM Power 9 systems.  Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
> 
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
> ---
> v2:
> * Removed ifdef's for PPC since the rte_smp_*mb() macros are already
>   customized for each CPU architecture
> 
>  app/test/test_barrier.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
> index a022708..0bf82cf 100644
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -92,12 +92,14 @@ struct lcore_plock_test {
>  	other = self ^ 1;
> 
>  	l->flag[self] = 1;
> +	rte_smp_wmb();
>  	l->victim = self;
> 
>  	store_load_barrier(l->utype);
> 
>  	while (l->flag[other] == 1 && l->victim == self)
>  		rte_pause();
> +	rte_smp_rmb();
>  }
> 
>  static void
> --

Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

> 1.8.3.1


  parent reply	other threads:[~2019-05-07 10:40 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-06 19:24 David Christensen
2019-05-06 19:24 ` David Christensen
2019-05-07 10:40 ` Ananyev, Konstantin [this message]
2019-05-07 10:40   ` Ananyev, Konstantin

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