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From: David Christensen <drc@linux.vnet.ibm.com>
To: dev@dpdk.org
Cc: David Christensen <drc@linux.vnet.ibm.com>
Subject: [dpdk-dev] [PATCH v3 4/4] test: fix memory barrier test failure on power CPUs
Date: Wed,  8 May 2019 16:02:43 -0500	[thread overview]
Message-ID: <1557349363-26213-1-git-send-email-drc@linux.vnet.ibm.com> (raw)
Message-ID: <20190508210243.ZAkxO0cz4QDUJL_IvcGbJaZwT0NiiKLnI1KmwZfHkjk@z> (raw)

The memory barrier test fails on IBM Power 9 systems.  Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.

Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
  customized for each CPU architecture
v3:
* None
---
 app/test/test_barrier.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ struct lcore_plock_test {
 	other = self ^ 1;
 
 	l->flag[self] = 1;
+	rte_smp_wmb();
 	l->victim = self;
 
 	store_load_barrier(l->utype);
 
 	while (l->flag[other] == 1 && l->victim == self)
 		rte_pause();
+	rte_smp_rmb();
 }
 
 static void
-- 
1.8.3.1


             reply	other threads:[~2019-05-08 21:02 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-08 21:02 David Christensen [this message]
2019-05-08 21:02 ` David Christensen

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