From: Gavin Hu <gavin.hu@arm.com>
To: dev@dpdk.org
Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,
rasland@mellanox.com, drc@linux.vnet.ibm.com,
bruce.richardson@intel.com, konstantin.ananyev@intel.com,
matan@mellanox.com, shahafs@mellanox.com,
viacheslavo@mellanox.com, jerinj@marvell.com,
Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com,
phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com,
stable@dpdk.org
Subject: [dpdk-stable] [PATCH RFC v1 3/6] net/mlx5: add missing barrier
Date: Thu, 13 Feb 2020 20:38:51 +0800 [thread overview]
Message-ID: <20200213123854.203566-4-gavin.hu@arm.com> (raw)
In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com>
To keep order of the modification of RX queue descriptor(rxq->cq_db) and
the CQ doorbell register, a rte_cio_wmb barrier is required.
The situation was rescued by the stronger than required barrier in the
mlx5_uar_write64, it becomes a must when the barrier is relaxed.
Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems")
Cc: stable@dpdk.org
Suggested-by: Phil Yang <phil.yang@arm.com>
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
---
drivers/net/mlx5/mlx5_rxq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index dc0fd8211..2d1b153a3 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -856,7 +856,8 @@ mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
doorbell = (uint64_t)doorbell_hi << 32;
doorbell |= rxq->cqn;
rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
- mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
+ rte_cio_wmb();
+ mlx5_uar_write64_relaxed(rte_cpu_to_be_64(doorbell),
cq_db_reg, rxq->uar_lock_cq);
}
--
2.17.1
next prev parent reply other threads:[~2020-02-13 12:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200410164127.54229-1-gavin.hu@arm.com>
[not found] ` <20200213123854.203566-1-gavin.hu@arm.com>
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 1/6] net/mlx5: relax the barrier for UAR write Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 2/6] net/mlx5: use cio barrier before the BF WQE Gavin Hu
2020-02-13 12:38 ` Gavin Hu [this message]
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 5/6] net/mlx5: non-cacheable mapping defaulted for aarch64 Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 6/6] net/mlx5: relaxed ordering for multi-packet RQ buffer refcnt Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 3/7] net/mlx5: relax barrier to order UAR writes on aarch64 Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 4/7] net/mlx5: relax barrier for aarch64 Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 6/7] net/mlx5: relax ordering for multi-packet RQ buffer refcnt Gavin Hu
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