From: Alexander Kozyrev <akozyrev@nvidia.com>
To: dev@dpdk.org
Cc: stable@dpdk.org, rasland@nvidia.com, viacheslavo@nvidia.com
Subject: [dpdk-stable] [PATCH] net/mlx5: fix modify field action endianness
Date: Fri, 2 Apr 2021 02:07:41 +0000 [thread overview]
Message-ID: <20210402020741.25715-1-akozyrev@nvidia.com> (raw)
Converting modify_field action masks to the big endian format is wrong
for small (less than 4 bytes) fields. Use the BE conversions appropriate
for a field size, not rte_cpu_to_be_32 for everything.
Fixes: 7ffda9dbed ("net/mlx5: adjust modify field action endianness")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 39 +++++++++++----------------------
1 file changed, 13 insertions(+), 26 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 533dadf07b..bf1ab1b712 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1360,8 +1360,7 @@ mlx5_flow_field_id_to_modify_info
}
info[idx] = (struct field_modify_info){2, 4 * idx,
MLX5_MODI_OUT_DMAC_15_0};
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
@@ -1390,8 +1389,7 @@ mlx5_flow_field_id_to_modify_info
}
info[idx] = (struct field_modify_info){2, 4 * idx,
MLX5_MODI_OUT_SMAC_15_0};
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
@@ -1407,29 +1405,25 @@ mlx5_flow_field_id_to_modify_info
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_FIRST_VID};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x00000fff >>
- (12 - width));
+ mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
break;
case RTE_FLOW_FIELD_MAC_TYPE:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_ETHERTYPE};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
break;
case RTE_FLOW_FIELD_IPV4_DSCP:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IP_DSCP};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000003f >>
- (6 - width));
+ mask[idx] = 0x3f >> (6 - width);
break;
case RTE_FLOW_FIELD_IPV4_TTL:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IPV4_TTL};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x000000ff >>
- (8 - width));
+ mask[idx] = 0xff >> (8 - width);
break;
case RTE_FLOW_FIELD_IPV4_SRC:
info[idx] = (struct field_modify_info){4, 0,
@@ -1449,15 +1443,13 @@ mlx5_flow_field_id_to_modify_info
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IP_DSCP};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000003f >>
- (6 - width));
+ mask[idx] = 0x3f >> (6 - width);
break;
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IPV6_HOPLIMIT};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x000000ff >>
- (8 - width));
+ mask[idx] = 0xff >> (8 - width);
break;
case RTE_FLOW_FIELD_IPV6_SRC:
if (mask) {
@@ -1605,15 +1597,13 @@ mlx5_flow_field_id_to_modify_info
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_TCP_SPORT};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
break;
case RTE_FLOW_FIELD_TCP_PORT_DST:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_TCP_DPORT};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
break;
case RTE_FLOW_FIELD_TCP_SEQ_NUM:
info[idx] = (struct field_modify_info){4, 0,
@@ -1633,22 +1623,19 @@ mlx5_flow_field_id_to_modify_info
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_TCP_FLAGS};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000003f >>
- (6 - width));
+ mask[idx] = 0x3f >> (6 - width);
break;
case RTE_FLOW_FIELD_UDP_PORT_SRC:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_UDP_SPORT};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
break;
case RTE_FLOW_FIELD_UDP_PORT_DST:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_UDP_DPORT};
if (mask)
- mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
- (16 - width));
+ mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
break;
case RTE_FLOW_FIELD_VXLAN_VNI:
/* not supported yet */
--
2.24.1
next reply other threads:[~2021-04-02 2:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 2:07 Alexander Kozyrev [this message]
2021-04-07 15:06 ` Slava Ovsiienko
2021-04-11 7:22 ` Raslan Darawsheh
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