From: Harman Kalra <hkalra@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: Harman Kalra <hkalra@marvell.com>
Subject: [dpdk-dev] [PATCH 2/2] common/cnxk: cq overflow issue
Date: Tue, 21 Sep 2021 16:30:38 +0530 [thread overview]
Message-ID: <20210921110038.115560-2-hkalra@marvell.com> (raw)
In-Reply-To: <20210921110038.115560-1-hkalra@marvell.com>
An issue exists on some HW revisions whereby if a CQ overflows
NIX may have undefined behavior, e.g. free incorrect buffers.
Implementing a workaround for this known HW issue.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
drivers/common/cnxk/roc_nix_priv.h | 3 ++-
drivers/common/cnxk/roc_nix_queue.c | 18 +++++++++++++++---
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 9dc0c88a6f..1bd1b6a36b 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -17,7 +17,8 @@
/* Apply BP/DROP when CQ is 95% full */
#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
-#define NIX_RQ_AURA_THRESH(x) (((x) * 95) / 100)
+#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
+#define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100)
/* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
#define CQ_CQE_THRESH_DEFAULT 0x1ULL
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 76e439e7a9..d7c4844d69 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -2,6 +2,8 @@
* Copyright(C) 2021 Marvell.
*/
+#include <math.h>
+
#include "roc_api.h"
#include "roc_priv.h"
@@ -435,7 +437,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
cq->status = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS);
cq->wdata = (uint64_t)cq->qid << 32;
cq->roc_nix = roc_nix;
- cq->drop_thresh = NIX_CQ_THRESH_LEVEL;
/* CQE of W16 */
desc_sz = cq->nb_desc * NIX_CQ_ENTRY_SZ;
@@ -476,8 +477,19 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
cq_ctx->cint_idx = cq->qid;
- cq_ctx->drop = cq->drop_thresh;
- cq_ctx->drop_ena = 1;
+ if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
+ const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
+ uint16_t min_rx_drop;
+
+ min_rx_drop = ceil(rx_cq_skid / (float)cq->nb_desc);
+ cq_ctx->drop = min_rx_drop;
+ cq_ctx->drop_ena = 1;
+ cq->drop_thresh = min_rx_drop;
+ } else {
+ cq->drop_thresh = NIX_CQ_THRESH_LEVEL;
+ cq_ctx->drop = cq->drop_thresh;
+ cq_ctx->drop_ena = 1;
+ }
/* TX pause frames enable flow ctrl on RX side */
if (nix->tx_pause) {
--
2.18.0
next prev parent reply other threads:[~2021-09-21 11:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 11:00 [dpdk-dev] [PATCH 1/2] common/cnxk: clear rvum interrupts Harman Kalra
2021-09-21 11:00 ` Harman Kalra [this message]
2021-09-30 15:53 ` Jerin Jacob
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