From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,
"Shijith Thotton" <sthotton@marvell.com>
Cc: <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH 2/3] event/cnxk: reduce workslot memory consumption
Date: Mon, 4 Oct 2021 14:07:37 +0530 [thread overview]
Message-ID: <20211004083738.13386-2-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20211004083738.13386-1-pbhagavatula@marvell.com>
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
SSO group base addresses are always are always contiguous we
need not store all the base addresses in workslot memory, instead
just store the base address and compute the group address offset
when required.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
drivers/event/cnxk/cn10k_eventdev.c | 5 ++---
drivers/event/cnxk/cn10k_worker.h | 3 ++-
drivers/event/cnxk/cn9k_eventdev.c | 8 +++-----
drivers/event/cnxk/cn9k_worker.h | 6 ++++--
drivers/event/cnxk/cnxk_eventdev.c | 15 ++++++---------
drivers/event/cnxk/cnxk_eventdev.h | 8 ++++----
6 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
index c2729a2c48..49bdd14208 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -91,14 +91,13 @@ cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
}
static void
-cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
+cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
{
struct cnxk_sso_evdev *dev = arg;
struct cn10k_sso_hws *ws = hws;
uint64_t val;
- rte_memcpy(ws->grps_base, grps_base,
- sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
+ ws->grp_base = grp_base;
ws->fc_mem = (uint64_t *)dev->fc_iova;
ws->xaq_lmt = dev->xaq_lmt;
diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index 657ab91ac8..f8331e88d7 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -30,7 +30,8 @@ cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)
if (ws->xaq_lmt <= *ws->fc_mem)
return 0;
- cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);
+ cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
+ ws->grp_base + (grp << 12));
return 1;
}
diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c
index 3a20b099ae..9886720310 100644
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -87,7 +87,7 @@ cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
}
static void
-cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
+cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
{
struct cnxk_sso_evdev *dev = arg;
struct cn9k_sso_hws_dual *dws;
@@ -98,8 +98,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
val = NSEC2USEC(dev->deq_tmo_ns) - 1;
if (dev->dual_ws) {
dws = hws;
- rte_memcpy(dws->grps_base, grps_base,
- sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
+ dws->grp_base = grp_base;
dws->fc_mem = (uint64_t *)dev->fc_iova;
dws->xaq_lmt = dev->xaq_lmt;
@@ -107,8 +106,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);
} else {
ws = hws;
- rte_memcpy(ws->grps_base, grps_base,
- sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
+ ws->grp_base = grp_base;
ws->fc_mem = (uint64_t *)dev->fc_iova;
ws->xaq_lmt = dev->xaq_lmt;
diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h
index 6be9be0b47..320e39da7b 100644
--- a/drivers/event/cnxk/cn9k_worker.h
+++ b/drivers/event/cnxk/cn9k_worker.h
@@ -31,7 +31,8 @@ cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)
if (ws->xaq_lmt <= *ws->fc_mem)
return 0;
- cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);
+ cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
+ ws->grp_base + (grp << 12));
return 1;
}
@@ -108,7 +109,8 @@ cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws,
if (dws->xaq_lmt <= *dws->fc_mem)
return 0;
- cnxk_sso_hws_add_work(event_ptr, tag, new_tt, dws->grps_base[grp]);
+ cnxk_sso_hws_add_work(event_ptr, tag, new_tt,
+ dws->grp_base + (grp << 12));
return 1;
}
diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c
index 84bf8cb6d1..c127034d37 100644
--- a/drivers/event/cnxk/cnxk_eventdev.c
+++ b/drivers/event/cnxk/cnxk_eventdev.c
@@ -332,8 +332,7 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
cnxk_sso_hws_setup_t hws_setup_fn)
{
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
- uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0};
- uint16_t q;
+ uintptr_t grp_base = 0;
plt_sso_dbg("Port=%d", port_id);
if (event_dev->data->ports[port_id] == NULL) {
@@ -341,15 +340,13 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
return -EINVAL;
}
- for (q = 0; q < dev->nb_event_queues; q++) {
- grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q);
- if (grps_base[q] == 0) {
- plt_err("Failed to get grp[%d] base addr", q);
- return -EINVAL;
- }
+ grp_base = roc_sso_hwgrp_base_get(&dev->sso, 0);
+ if (grp_base == 0) {
+ plt_err("Failed to get grp base addr");
+ return -EINVAL;
}
- hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base);
+ hws_setup_fn(dev, event_dev->data->ports[port_id], grp_base);
plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
rte_mb();
diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h
index ccd09b1d82..ce9f965691 100644
--- a/drivers/event/cnxk/cnxk_eventdev.h
+++ b/drivers/event/cnxk/cnxk_eventdev.h
@@ -61,7 +61,7 @@
} while (0)
typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
-typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
+typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t grp_base);
typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,
uint16_t nb_link);
@@ -129,7 +129,7 @@ struct cn10k_sso_hws {
/* Add Work Fastpath data */
uint64_t xaq_lmt __rte_cache_aligned;
uint64_t *fc_mem;
- uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
+ uintptr_t grp_base;
/* Tx Fastpath data */
uint64_t tx_base __rte_cache_aligned;
uintptr_t lmt_base;
@@ -157,7 +157,7 @@ struct cn9k_sso_hws {
/* Add Work Fastpath data */
uint64_t xaq_lmt __rte_cache_aligned;
uint64_t *fc_mem;
- uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
+ uintptr_t grp_base;
/* Tx Fastpath data */
uint64_t base __rte_cache_aligned;
uint8_t tx_adptr_data[];
@@ -179,7 +179,7 @@ struct cn9k_sso_hws_dual {
/* Add Work Fastpath data */
uint64_t xaq_lmt __rte_cache_aligned;
uint64_t *fc_mem;
- uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
+ uintptr_t grp_base;
/* Tx Fastpath data */
uint64_t base[2] __rte_cache_aligned;
uint8_t tx_adptr_data[];
--
2.33.0
next prev parent reply other threads:[~2021-10-04 8:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 8:37 [dpdk-dev] [PATCH 1/3] event/cnxk: fix packet Tx overflow pbhagavatula
2021-10-04 8:37 ` pbhagavatula [this message]
2021-10-04 8:37 ` [dpdk-dev] [PATCH 3/3] event/cnxk: rework enqueue path pbhagavatula
2021-10-30 13:36 ` [dpdk-dev] [PATCH 1/3] event/cnxk: fix packet Tx overflow Jerin Jacob
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