From: Min Zhou <zhoumin@loongson.cn>
To: thomas@monjalon.net, david.marchand@redhat.com,
bruce.richardson@intel.com, anatoly.burakov@intel.com,
qiming.yang@intel.com, Yuying.Zhang@intel.com,
jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru
Cc: dev@dpdk.org, maobibo@loongson.cn
Subject: [PATCH v4 03/24] eal/loongarch: add cpu cycle operations for LoongArch
Date: Thu, 21 Jul 2022 20:51:23 +0800 [thread overview]
Message-ID: <20220721125144.4028113-4-zhoumin@loongson.cn> (raw)
In-Reply-To: <20220721125144.4028113-1-zhoumin@loongson.cn>
This patch adds architecture specific cpu cycle operations for
LoongArch. The RDTIME.D instruction is used to read constant
frequency timer information including counter value. The CPUCFG
instruction is used to dynamically identify which features of
LoongArch are implemented in the running processor during the
execution of the software. We can use this instruction to calculate
the frequency used by the timer.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
lib/eal/loongarch/include/rte_cycles.h | 53 ++++++++++++++++++++++++++
lib/eal/loongarch/rte_cycles.c | 45 ++++++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_cycles.h
create mode 100644 lib/eal/loongarch/rte_cycles.c
diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h
new file mode 100644
index 0000000000..1f8f957faf
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_cycles.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_CYCLES_LOONGARCH_H_
+#define _RTE_CYCLES_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+static inline uint64_t
+get_cycle_count(void)
+{
+ uint64_t count;
+
+ __asm__ __volatile__ (
+ "rdtime.d %[cycles], $zero\n"
+ : [cycles] "=r" (count)
+ ::
+ );
+ return count;
+}
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ * The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+ return get_cycle_count();
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+ rte_mb();
+ return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c
new file mode 100644
index 0000000000..582601d335
--- /dev/null
+++ b/lib/eal/loongarch/rte_cycles.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "eal_private.h"
+
+#define LOONGARCH_CPUCFG4 0x4
+#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF
+#define CPUCFG4_CCFREQ_SHIFT 0
+
+#define LOONGARCH_CPUCFG5 0x5
+#define CPUCFG5_CCMUL_MASK 0xFFFF
+#define CPUCFG5_CCMUL_SHIFT 0
+
+#define CPUCFG5_CCDIV_MASK 0xFFFF0000
+#define CPUCFG5_CCDIV_SHIFT 16
+
+static __rte_noinline uint32_t
+read_cpucfg(int arg)
+{
+ int ret = 0;
+
+ __asm__ __volatile__ (
+ "cpucfg %[var], %[index]\n"
+ : [var]"=r"(ret)
+ : [index]"r"(arg)
+ :
+ );
+
+ return ret;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+ uint32_t base_freq, mul_factor, div_factor;
+
+ base_freq = read_cpucfg(LOONGARCH_CPUCFG4);
+ mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>
+ CPUCFG5_CCMUL_SHIFT;
+ div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>
+ CPUCFG5_CCDIV_SHIFT;
+
+ return base_freq * mul_factor / div_factor;
+}
--
2.31.1
next prev parent reply other threads:[~2022-07-21 12:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-21 12:51 [PATCH v4 00/24] Support LoongArch architecture Min Zhou
2022-07-21 12:51 ` [PATCH v4 01/24] eal/loongarch: add atomic operations for LoongArch Min Zhou
2022-07-21 12:51 ` [PATCH v4 02/24] eal/loongarch: add byte order " Min Zhou
2022-07-21 12:51 ` Min Zhou [this message]
2022-07-21 12:51 ` [PATCH v4 04/24] eal/loongarch: add prefetch " Min Zhou
2022-07-21 12:51 ` [PATCH v4 05/24] eal/loongarch: add spinlock " Min Zhou
2022-07-21 12:51 ` [PATCH v4 06/24] eal/loongarch: add cpu flag checks " Min Zhou
2022-07-21 12:51 ` [PATCH v4 07/24] eal/loongarch: add dummy vector memcpy " Min Zhou
2022-07-21 12:51 ` [PATCH v4 08/24] eal/loongarch: add io operations " Min Zhou
2022-07-21 12:51 ` [PATCH v4 09/24] eal/loongarch: add mcslock " Min Zhou
2022-07-21 12:51 ` [PATCH v4 10/24] eal/loongarch: add pause " Min Zhou
2022-07-21 12:51 ` [PATCH v4 11/24] eal/loongarch: add pflock " Min Zhou
2022-07-21 12:51 ` [PATCH v4 12/24] eal/loongarch: add rwlock " Min Zhou
2022-07-21 12:51 ` [PATCH v4 13/24] eal/loongarch: add ticketlock " Min Zhou
2022-07-21 12:51 ` [PATCH v4 14/24] eal/loongarch: add power " Min Zhou
2022-07-21 12:51 ` [PATCH v4 15/24] eal/loongarch: add hypervisor " Min Zhou
2022-07-21 12:51 ` [PATCH v4 16/24] mem: add huge page size definition " Min Zhou
2022-07-21 12:51 ` [PATCH v4 17/24] eal/linux: set eal base address " Min Zhou
2022-07-21 12:51 ` [PATCH v4 18/24] meson: introduce LoongArch architecture Min Zhou
2022-07-21 12:51 ` [PATCH v4 19/24] test/xmmt_ops: add dummy vector implementation for LoongArch Min Zhou
2022-07-21 12:51 ` [PATCH v4 20/24] ixgbe: " Min Zhou
2022-07-21 12:51 ` [PATCH v4 21/24] i40e: " Min Zhou
2022-07-21 12:51 ` [PATCH v4 22/24] tap: add system call number " Min Zhou
2022-07-21 12:51 ` [PATCH v4 23/24] memif: " Min Zhou
2022-07-21 12:51 ` [PATCH v4 24/24] maintainers: claim responsibility " Min Zhou
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