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From: Michael Piszczek <mpiszczek@ddn.com>
To: dev@dpdk.org
Cc: Vipin.Varghese@amd.com, Michael Piszczek <mpiszczek@ddn.com>
Subject: [PATCH v3] pci: read amd iommu virtual address width
Date: Mon, 10 Oct 2022 23:47:19 +0200	[thread overview]
Message-ID: <20221010214720.766459-1-mpiszczek@ddn.com> (raw)
In-Reply-To: <20220912160157.3642968-2-mpiszczek@ddn.com>

Add code to read the virtual address width for AMD processors.

Signed-off-by: Michael Piszczek <mpiszczek@ddn.com>
---
 drivers/bus/pci/linux/pci.c | 47 +++++++++++++++++++++++--------------
 1 file changed, 30 insertions(+), 17 deletions(-)

diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index e521459870..8c6082ee7a 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -492,15 +492,18 @@ rte_pci_scan(void)
 }
 
 #if defined(RTE_ARCH_X86)
+
 bool
 pci_device_iommu_support_va(const struct rte_pci_device *dev)
 {
 #define VTD_CAP_MGAW_SHIFT	16
 #define VTD_CAP_MGAW_MASK	(0x3fULL << VTD_CAP_MGAW_SHIFT)
+#define RD_AMD_CAP_VASIZE_SHIFT 15
+#define RD_AMD_CAP_VASIZE_MASK  (0x7F << RD_AMD_CAP_VASIZE_SHIFT)
 	const struct rte_pci_addr *addr = &dev->addr;
 	char filename[PATH_MAX];
 	FILE *fp;
-	uint64_t mgaw, vtd_cap_reg = 0;
+	uint64_t mgaw, cap_reg = 0;
 
 	snprintf(filename, sizeof(filename),
 		 "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
@@ -508,26 +511,36 @@ pci_device_iommu_support_va(const struct rte_pci_device *dev)
 		 addr->function);
 
 	fp = fopen(filename, "r");
-	if (fp == NULL) {
-		/* We don't have an Intel IOMMU, assume VA supported */
-		if (errno == ENOENT)
-			return true;
-
-		RTE_LOG(ERR, EAL, "%s(): can't open %s: %s\n",
-			__func__, filename, strerror(errno));
-		return false;
-	}
+	if (fp != NULL) {
+		/* We have an Intel IOMMU */
+		if (fscanf(fp, "%" PRIx64, &cap_reg) != 1) {
+			   RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
+			fclose(fp);
+			return false;
+		}
 
-	/* We have an Intel IOMMU */
-	if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
-		RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
 		fclose(fp);
-		return false;
+		mgaw = ((cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
 	}
+	else {
+		snprintf(filename, sizeof(filename),
+			 "%s/" PCI_PRI_FMT "/iommu/amd-iommu/cap",
+			  rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
+			  addr->function);
+
+		fp = fopen(filename, "r");
+		if (fp != NULL) {
+			/* We have an Amd IOMMU */
+			if (fscanf(fp, "%" PRIx64, &cap_reg) != 1) {
+				   RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
+				fclose(fp);
+				return false;
+			}
 
-	fclose(fp);
-
-	mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
+			fclose(fp);
+			mgaw = ((cap_reg & RD_AMD_CAP_VASIZE_MASK) >> RD_AMD_CAP_VASIZE_SHIFT) + 1;
+		}
+	}
 
 	/*
 	 * Assuming there is no limitation by now. We can not know at this point
-- 
2.34.1

next prev parent reply	other threads:[~2022-10-11  1:51 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-12 16:01 [PATCH 0/1] " Michael Piszczek
2022-09-12 16:01 ` [PATCH 1/1] " Michael Piszczek
2022-09-14 13:49   ` [PATCH v2] " Michael Piszczek
2022-10-03  7:48     ` David Marchand
2022-10-10 13:12       ` Varghese, Vipin
2022-10-10 21:47   ` Michael Piszczek [this message]
2022-10-10 21:47     ` [PATCH v3] " Michael Piszczek
2022-10-11 22:00     ` Ferruh Yigit
2022-10-11 14:08   ` [PATCH v4] " Michael Piszczek
2022-10-11 14:08     ` Michael Piszczek
2022-10-12  9:18     ` Ferruh Yigit
2022-10-12 15:15     ` Stephen Hemminger
2022-10-13 18:16   ` [PATCH v5] " Michael Piszczek
2022-10-13 18:16     ` Michael Piszczek
2022-10-24 18:09       ` Stephen Hemminger
2022-10-25  7:56         ` Ferruh Yigit
2022-10-17 15:45   ` [PATCH v6] " Michael Piszczek
2022-10-17 15:45     ` Michael Piszczek
2022-10-25 11:54       ` David Marchand
2023-08-08  7:31         ` David Marchand
2023-08-08 13:53           ` Michael Piszczek

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