From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: <dev@dpdk.org>
Cc: <matan@nvidia.com>, <rasland@nvidia.com>, <valex@nvidia.com>
Subject: [PATCH] net/mlx5/hws: fix timestamp format on Tx queue creation
Date: Tue, 8 Nov 2022 20:56:50 +0200 [thread overview]
Message-ID: <20221108185650.15489-1-viacheslavo@nvidia.com> (raw)
The NIC since 6DX supports multiple timestamp formats
in CQEs configured via firmware. If real time timestamp
format has been configured the correct attributes should
be specified on queue creation via DevX. These attributes
setting was missed on steering queue creation and hardware
steering initialization failed.
Fixes: 3eb748869d2d ("net/mlx5/hws: add send layer")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/net/mlx5/hws/mlx5dr_cmd.c | 7 +++++++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 3 +++
drivers/net/mlx5/hws/mlx5dr_send.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index da8cc3d265..ae6637475c 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -674,6 +674,7 @@ mlx5dr_cmd_sq_create(struct ibv_context *ctx,
MLX5_SET(sqc, sqc, cqn, attr->cqn);
MLX5_SET(sqc, sqc, flush_in_error_en, 1);
MLX5_SET(sqc, sqc, non_wire, 1);
+ MLX5_SET(sqc, sqc, ts_format, attr->ts_format);
MLX5_SET(wq, wqc, wq_type, MLX5_WQ_TYPE_CYCLIC);
MLX5_SET(wq, wqc, pd, attr->pdn);
MLX5_SET(wq, wqc, uar_page, attr->page_id);
@@ -682,6 +683,7 @@ mlx5dr_cmd_sq_create(struct ibv_context *ctx,
MLX5_SET(wq, wqc, dbr_umem_id, attr->dbr_id);
MLX5_SET(wq, wqc, wq_umem_id, attr->wq_id);
+
devx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));
if (!devx_obj->obj) {
simple_free(devx_obj);
@@ -763,6 +765,11 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
MLX5_GET64(query_hca_cap_out, out,
capability.cmd_hca_cap.match_definer_format_supported);
+ caps->rq_ts_format = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.rq_ts_format);
+ caps->sq_ts_format = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.sq_ts_format);
+
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 2548b2b238..d29ed55adc 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -121,6 +121,7 @@ struct mlx5dr_cmd_sq_create_attr {
uint32_t dbr_id;
uint32_t wq_id;
uint32_t log_wq_sz;
+ uint32_t ts_format;
};
struct mlx5dr_cmd_query_ft_caps {
@@ -161,6 +162,8 @@ struct mlx5dr_cmd_query_caps {
uint8_t log_header_modify_argument_max_alloc;
uint64_t definer_format_sup;
uint32_t trivial_match_definer;
+ uint8_t rq_ts_format;
+ uint8_t sq_ts_format;
char fw_ver[64];
};
diff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c
index 1e9953a38f..06d4a7e5c5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_send.c
+++ b/drivers/net/mlx5/hws/mlx5dr_send.c
@@ -492,6 +492,9 @@ static int mlx5dr_send_ring_create_sq_obj(struct mlx5dr_context *ctx,
attr.dbr_id = sq->db_umem->umem_id;
attr.wq_id = sq->buf_umem->umem_id;
attr.log_wq_sz = log_wq_sz;
+ attr.ts_format = (ctx->caps->sq_ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR) ?
+ MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
sq->obj = mlx5dr_cmd_sq_create(ctx->ibv_ctx, &attr);
if (!sq->obj)
--
2.18.1
next reply other threads:[~2022-11-08 18:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 18:56 Viacheslav Ovsiienko [this message]
2022-11-09 7:57 ` [PATCH v2] " Viacheslav Ovsiienko
2022-11-09 9:55 ` Raslan Darawsheh
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