From: Simei Su <simei.su@intel.com>
To: qi.z.zhang@intel.com, junfeng.guo@intel.com
Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su <simei.su@intel.com>
Subject: [PATCH v2 1/2] net/igc/base: expose packet pacing registers
Date: Wed, 1 Feb 2023 15:30:13 +0800 [thread overview]
Message-ID: <20230201073014.431924-2-simei.su@intel.com> (raw)
In-Reply-To: <20230201073014.431924-1-simei.su@intel.com>
Add definitions for packet pacing(launch time offloading) related
registers.
Signed-off-by: Simei Su <simei.su@intel.com>
---
drivers/net/igc/base/igc_defines.h | 9 +++++++++
drivers/net/igc/base/igc_regs.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h
index dd7330a..280570b 100644
--- a/drivers/net/igc/base/igc_defines.h
+++ b/drivers/net/igc/base/igc_defines.h
@@ -188,6 +188,15 @@
#define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */
#define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
+#define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
+#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */
+
+/* Transmit Scheduling */
+#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
+#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008
+
+#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
+
/* Use byte values for the following shift parameters
* Usage:
* psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) &
diff --git a/drivers/net/igc/base/igc_regs.h b/drivers/net/igc/base/igc_regs.h
index d424387..e423814 100644
--- a/drivers/net/igc/base/igc_regs.h
+++ b/drivers/net/igc/base/igc_regs.h
@@ -602,6 +602,14 @@
#define IGC_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
#define IGC_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
+#define IGC_QBVCYCLET 0x331C
+#define IGC_QBVCYCLET_S 0x3320
+#define IGC_STQT(_n) (0x3324 + 0x4 * (_n))
+#define IGC_ENDQT(_n) (0x3334 + 0x4 * (_n))
+#define IGC_TXQCTL(_n) (0x3344 + 0x4 * (_n))
+#define IGC_BASET_L 0x3314
+#define IGC_BASET_H 0x3318
+
/* Filtering Registers */
#define IGC_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
#define IGC_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
--
2.9.5
next prev parent reply other threads:[~2023-02-01 7:31 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 3:47 [PATCH 0/2] net/igc: support Tx timestamp offload Simei Su
2022-12-20 3:47 ` [PATCH 1/2] net/igc/base: " Simei Su
2022-12-20 3:47 ` [PATCH 2/2] net/igc: enable " Simei Su
2023-02-01 7:30 ` [PATCH v2 0/2] net/igc: support launch time offloading Simei Su
2023-02-01 7:30 ` Simei Su [this message]
2023-02-01 7:30 ` [PATCH v2 2/2] net/igc: enable " Simei Su
2023-02-01 8:34 ` Zhang, Qi Z
2023-02-01 8:46 ` [PATCH v2 0/2] net/igc: support " Morten Brørup
2023-02-02 7:17 ` [PATCH v3 " Simei Su
2023-02-02 7:18 ` [PATCH v3 1/2] net/igc/base: expose packet pacing registers Simei Su
2023-02-02 7:18 ` [PATCH v3 2/2] net/igc: enable launch time offloading Simei Su
2023-02-03 0:30 ` Stephen Hemminger
2023-02-03 3:22 ` Su, Simei
2023-02-02 8:46 ` [PATCH v3 0/2] net/igc: support " Zhang, Qi Z
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