From: Qiming Yang <qiming.yang@intel.com>
To: dev@dpdk.org
Cc: qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,
Ashish Shah <ashish.n.shah@intel.com>
Subject: [PATCH 04/30] net/ice/base: update flow seg fields to declared bitmaps
Date: Thu, 27 Apr 2023 06:19:35 +0000 [thread overview]
Message-ID: <20230427062001.478032-5-qiming.yang@intel.com> (raw)
In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com>
ice_flow_seg_info fields match and range are being used with bit
operations but not declared as bitmaps. This can cause issues when
casting values greater than 32. This change is to declare them as proper
bitmaps so that the bitmap operations can function as intended.
Signed-off-by: Ashish Shah <ashish.n.shah@intel.com>
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 74 +++++++++++++++++++++++----------
drivers/net/ice/base/ice_flow.h | 6 ++-
2 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 5254ee27ed..8db394471c 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1132,6 +1132,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
}
+
if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
(hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
src = i ?
@@ -1371,7 +1372,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw,
*/
static enum ice_status
ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
- u8 seg, enum ice_flow_field fld, u64 match)
+ u8 seg, enum ice_flow_field fld, ice_bitmap_t *match)
{
enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX;
u8 fv_words = (u8)hw->blk[params->blk].es.fvw;
@@ -1420,7 +1421,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
/* If the sibling field is also included, that field's
* mask needs to be included.
*/
- if (match & BIT(sib))
+ if (ice_is_bit_set(match, sib))
sib_mask = ice_flds_info[sib].mask;
break;
case ICE_FLOW_FIELD_IDX_IPV6_TTL:
@@ -1451,7 +1452,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
/* If the sibling field is also included, that field's
* mask needs to be included.
*/
- if (match & BIT(sib))
+ if (ice_is_bit_set(match, sib))
sib_mask = ice_flds_info[sib].mask;
break;
case ICE_FLOW_FIELD_IDX_IPV4_SA:
@@ -1722,15 +1723,16 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,
}
for (i = 0; i < params->prof->segs_cnt; i++) {
- u64 match = params->prof->segs[i].match;
+ ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);
enum ice_flow_field j;
- ice_for_each_set_bit(j, (ice_bitmap_t *)&match,
- ICE_FLOW_FIELD_IDX_MAX) {
+ ice_cp_bitmap(match, params->prof->segs[i].match,
+ ICE_FLOW_FIELD_IDX_MAX);
+ ice_for_each_set_bit(j, match, ICE_FLOW_FIELD_IDX_MAX) {
status = ice_flow_xtract_fld(hw, params, i, j, match);
if (status)
return status;
- ice_clear_bit(j, (ice_bitmap_t *)&match);
+ ice_clear_bit(j, match);
}
/* Process raw matching bytes */
@@ -1789,7 +1791,7 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)
struct ice_flow_seg_info *seg = ¶ms->prof->segs[i];
u16 j;
- ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+ ice_for_each_set_bit(j, seg->match,
(u16)ICE_FLOW_FIELD_IDX_MAX) {
struct ice_flow_fld_info *fld = &seg->fields[j];
@@ -1932,7 +1934,10 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
for (i = 0; i < segs_cnt; i++)
if (segs[i].hdrs != p->segs[i].hdrs ||
((conds & ICE_FLOW_FIND_PROF_CHK_FLDS) &&
- segs[i].match != p->segs[i].match))
+ (ice_cmp_bitmap(segs[i].match,
+ p->segs[i].match,
+ ICE_FLOW_FIELD_IDX_MAX) ==
+ false)))
break;
/* A match is found if all segments are matched */
@@ -2432,7 +2437,7 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof)
struct ice_flow_seg_info *seg = &prof->segs[i];
u16 j;
- ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+ ice_for_each_set_bit(j, seg->match,
ICE_FLOW_FIELD_IDX_MAX) {
info = &seg->fields[j];
@@ -2601,7 +2606,8 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle,
idx = i;
params->es[idx].prot_id = prof->fv[i].proto_id;
params->es[idx].off = prof->fv[i].offset;
- params->mask[idx] = CPU_TO_BE16(prof->fv[i].msk);
+ params->mask[idx] = (((prof->fv[i].msk) << 8) & 0xff00) |
+ (((prof->fv[i].msk) >> 8) & 0x00ff);
}
switch (prof->flags) {
@@ -3002,7 +3008,7 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,
struct ice_flow_seg_info *seg = &prof->segs[i];
u16 j;
- ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,
+ ice_for_each_set_bit(j, seg->match,
(u16)ICE_FLOW_FIELD_IDX_MAX) {
struct ice_flow_fld_info *info = &seg->fields[j];
@@ -3534,7 +3540,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk,
if (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL)
return ICE_ERR_PARAM;
- entry = ICE_FLOW_ENTRY_PTR((intptr_t)entry_h);
+ entry = ICE_FLOW_ENTRY_PTR(entry_h);
/* Retain the pointer to the flow profile as the entry will be freed */
prof = entry->prof;
@@ -3576,11 +3582,9 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
enum ice_flow_fld_match_type field_type, u16 val_loc,
u16 mask_loc, u16 last_loc)
{
- u64 bit = BIT_ULL(fld);
-
- seg->match |= bit;
+ ice_set_bit(fld, seg->match);
if (field_type == ICE_FLOW_FLD_TYPE_RANGE)
- seg->range |= bit;
+ ice_set_bit(fld, seg->range);
seg->fields[fld].type = field_type;
seg->fields[fld].src.val = val_loc;
@@ -3741,7 +3745,7 @@ enum ice_status ice_flow_rem_vsi_prof(struct ice_hw *hw, enum ice_block blk, u16
}
#define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \
-(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_ETH_NON_IP | ICE_FLOW_SEG_HDR_VLAN)
+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)
@@ -3856,6 +3860,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_prof *p, *t;
enum ice_status status = ICE_SUCCESS;
+ u16 vsig;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
@@ -3865,7 +3870,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
ice_acquire_lock(&hw->rss_locks);
LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof,
- l_entry)
+ l_entry) {
+ int ret;
+
+ /* check if vsig is already removed */
+ ret = ice_vsig_find_vsi(hw, blk,
+ ice_get_hw_vsi_num(hw, vsi_handle),
+ &vsig);
+ if (!ret && !vsig)
+ break;
+
if (ice_is_bit_set(p->vsis, vsi_handle)) {
status = ice_flow_disassoc_prof(hw, blk, p, vsi_handle);
if (status)
@@ -3877,6 +3891,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
break;
}
}
+ }
ice_release_lock(&hw->rss_locks);
return status;
@@ -3918,6 +3933,14 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
{
enum ice_rss_cfg_hdr_type hdr_type;
struct ice_rss_cfg *r, *tmp;
+ u64 seg_match = 0;
+ u16 i;
+
+ /* convert match bitmap to u64 for hash field comparison */
+ ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,
+ ICE_FLOW_FIELD_IDX_MAX) {
+ seg_match |= 1ULL << i;
+ }
/* Search for RSS hash fields associated to the VSI that match the
* hash configurations associated to the flow profile. If found
@@ -3926,7 +3949,7 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
hdr_type = ice_get_rss_hdr_type(prof);
LIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head,
ice_rss_cfg, l_entry)
- if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&
+ if (r->hash.hash_flds == seg_match &&
r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&
r->hash.hdr_type == hdr_type) {
ice_clear_bit(vsi_handle, r->vsis);
@@ -3951,11 +3974,18 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
{
enum ice_rss_cfg_hdr_type hdr_type;
struct ice_rss_cfg *r, *rss_cfg;
+ u64 seg_match = 0;
+ u16 i;
+
+ ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,
+ ICE_FLOW_FIELD_IDX_MAX) {
+ seg_match |= 1ULL << i;
+ }
hdr_type = ice_get_rss_hdr_type(prof);
LIST_FOR_EACH_ENTRY(r, &hw->rss_list_head,
ice_rss_cfg, l_entry)
- if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&
+ if (r->hash.hash_flds == seg_match &&
r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&
r->hash.hdr_type == hdr_type) {
ice_set_bit(vsi_handle, r->vsis);
@@ -3966,7 +3996,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
if (!rss_cfg)
return ICE_ERR_NO_MEMORY;
- rss_cfg->hash.hash_flds = prof->segs[prof->segs_cnt - 1].match;
+ rss_cfg->hash.hash_flds = seg_match;
rss_cfg->hash.addl_hdrs = prof->segs[prof->segs_cnt - 1].hdrs;
rss_cfg->hash.hdr_type = hdr_type;
rss_cfg->hash.symm = prof->cfg.symm;
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 57e8e1f1df..1415f5ba87 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -452,8 +452,10 @@ struct ice_flow_seg_fld_raw {
struct ice_flow_seg_info {
u32 hdrs; /* Bitmask indicating protocol headers present */
- u64 match; /* Bitmask indicating header fields to be matched */
- u64 range; /* Bitmask indicating header fields matched as ranges */
+ /* Bitmask indicating header fields to be matched */
+ ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);
+ /* Bitmask indicating header fields matched as ranges */
+ ice_declare_bitmap(range, ICE_FLOW_FIELD_IDX_MAX);
struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];
--
2.25.1
next prev parent reply other threads:[~2023-04-27 6:38 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 6:19 [PATCH 00/30] net/ice/base: share code update Qiming Yang
2023-04-27 6:19 ` [PATCH 01/30] net/ice/base: updated copyright Qiming Yang
2023-04-27 6:19 ` [PATCH 02/30] net/ice/base: add flex array safe allocations Qiming Yang
2023-04-27 6:19 ` [PATCH 03/30] net/ice/base: remove unnecessary control queue array Qiming Yang
2024-03-05 18:05 ` [**EXTERNAL**] " Gudimetla, Leela Sankar
2023-04-27 6:19 ` Qiming Yang [this message]
2023-04-27 6:19 ` [PATCH 05/30] net/ice/base: clean up RSS LUT and fix media type Qiming Yang
2023-04-27 6:19 ` [PATCH 06/30] net/ice/base: add ability to set markid via switch filter Qiming Yang
2023-04-27 6:19 ` [PATCH 07/30] net/ice/base: add reading cap and ropo cap Qiming Yang
2023-04-27 6:19 ` [PATCH 08/30] net/ice/base: add function to read HW sensors Qiming Yang
2023-04-27 6:19 ` [PATCH 09/30] net/ice/base: add pre-allocate memory argument Qiming Yang
2023-04-27 6:19 ` [PATCH 10/30] net/ice/base: use coccinelle to instead macro Qiming Yang
2023-04-27 6:19 ` [PATCH 11/30] net/ice/base: add new fls function Qiming Yang
2023-04-27 6:19 ` [PATCH 12/30] net/ice/base: add E830 device ids Qiming Yang
2023-04-27 6:19 ` [PATCH 13/30] net/ice/base: add function to get rxq context Qiming Yang
2023-04-27 6:19 ` [PATCH 14/30] net/ice/base: removed no need 56G releated code Qiming Yang
2023-04-27 6:19 ` [PATCH 15/30] net/ice/base: allow skip main timer Qiming Yang
2023-04-27 6:19 ` [PATCH 16/30] net/ice/base: add E830 PTP init Qiming Yang
2023-04-27 6:19 ` [PATCH 17/30] net/ice/base: add C825X device support Qiming Yang
2023-04-27 6:19 ` [PATCH 18/30] net/ice/base: add VLAN TPID in switchdev Qiming Yang
2023-04-27 6:19 ` [PATCH 19/30] net/ice/base: reduce time to read Option ROM CIVD Qiming Yang
2023-04-27 6:19 ` [PATCH 20/30] net/ice/base: add L2TPv3 support for adv rules Qiming Yang
2023-04-27 6:19 ` [PATCH 21/30] net/ice/base: add PHY OFFSET READY register clear Qiming Yang
2023-04-27 6:19 ` [PATCH 22/30] net/ice/base: return CGU PLL config function params Qiming Yang
2023-04-27 6:19 ` [PATCH 23/30] net/ice/base: change method to get pca9575 handle Qiming Yang
2023-04-27 6:19 ` [PATCH 24/30] net/ice/base: cleanup timestamp registers correct Qiming Yang
2023-04-27 6:19 ` [PATCH 25/30] net/ice/base: add PPPoE hardware offload Qiming Yang
2023-04-27 6:19 ` [PATCH 26/30] net/ice/base: remove bypass mode Qiming Yang
2023-04-27 6:19 ` [PATCH 27/30] net/ice/base: support inner etype in switchdev Qiming Yang
2023-04-27 6:19 ` [PATCH 28/30] net/ice/base: use const array to store link modes Qiming Yang
2023-04-27 6:20 ` [PATCH 29/30] net/ice/base: introduce a new ID for E810 NIC Qiming Yang
2023-04-27 6:20 ` [PATCH 30/30] net/ice/base: fix Generic Checksum acronym Qiming Yang
2023-04-27 21:18 ` Greenwalt, Paul
2023-05-18 15:16 ` [PATCH v2 00/20] net/ice/base: code update Qiming Yang
2023-05-18 15:16 ` [PATCH v2 01/20] net/ice/base: updated copyright Qiming Yang
2023-05-18 15:16 ` [PATCH v2 02/20] net/ice/base: add NAC Topology device capability parser Qiming Yang
2023-05-18 15:16 ` [PATCH v2 03/20] net/ice/base: add new device for E810 Qiming Yang
2023-05-18 15:16 ` [PATCH v2 04/20] net/ice/base: fix incorrect defines for DCBx Qiming Yang
2023-05-18 15:16 ` [PATCH v2 05/20] net/ice/base: introduce a non-atomic function Qiming Yang
2023-05-18 15:16 ` [PATCH v2 06/20] net/ice/base: add missing AQ flag to AQ command Qiming Yang
2023-05-18 15:16 ` [PATCH v2 07/20] net/ice/base: add support for inner etype in switchdev Qiming Yang
2023-05-18 15:16 ` [PATCH v2 08/20] net/ice/base: add support for PPPoE hardware offload Qiming Yang
2023-05-18 15:16 ` [PATCH v2 09/20] net/ice/base: remove direction metadata for switchdev Qiming Yang
2023-05-18 15:16 ` [PATCH v2 10/20] net/ice/base: reduce time to read Option data Qiming Yang
2023-05-18 17:08 ` Keller, Jacob E
2023-05-18 15:16 ` [PATCH v2 11/20] net/ice/base: add support for VLAN TPID filters Qiming Yang
2023-05-18 15:16 ` [PATCH v2 12/20] net/ice/base: add C825-X device ID Qiming Yang
2023-05-18 15:16 ` [PATCH v2 13/20] net/ice/base: add function to get rxq context Qiming Yang
2023-05-18 15:16 ` [PATCH v2 14/20] net/ice/base: modify tunnel match mask Qiming Yang
2023-05-18 15:16 ` [PATCH v2 15/20] net/ice/base: check VSIG before disassociating VSI Qiming Yang
2023-05-18 15:16 ` [PATCH v2 16/20] net/ice/base: delete get field vector function Qiming Yang
2023-05-18 15:16 ` [PATCH v2 17/20] net/ice/base: update 3k-sign DDP support for E825C Qiming Yang
2023-05-18 15:16 ` [PATCH v2 18/20] net/ice/base: fix static analyzer bug Qiming Yang
2023-05-18 15:16 ` [PATCH v2 19/20] net/ice/base: offer memory config for schedual node Qiming Yang
2023-05-18 15:16 ` [PATCH v2 20/20] net/ice/base: add new AQ ro read HW sensors Qiming Yang
2023-05-23 2:12 ` [PATCH v2 00/20] net/ice/base: code update Zhang, Qi Z
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