From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,
maxime.coquelin@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>
Subject: [PATCH v1 03/11] test/bbdev: rename macros from acc200 to vrb
Date: Fri, 29 Sep 2023 11:13:20 -0700 [thread overview]
Message-ID: <20230929181328.104311-4-hernan.vargas@intel.com> (raw)
In-Reply-To: <20230929181328.104311-1-hernan.vargas@intel.com>
Renaming ACC200 macros to use generic intel vRAN Boost (VRB).
No functional impact.
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 91 ++++++++++++++++----------------
1 file changed, 45 insertions(+), 46 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index faea26c10eed..d4c001de0093 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -64,14 +64,14 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
-#define ACC200PF_DRIVER_NAME ("intel_acc200_pf")
-#define ACC200VF_DRIVER_NAME ("intel_acc200_vf")
-#define ACC200_QMGR_NUM_AQS 16
-#define ACC200_QMGR_NUM_QGS 2
-#define ACC200_QMGR_AQ_DEPTH 5
-#define ACC200_QMGR_INVALID_IDX -1
-#define ACC200_QMGR_RR 1
-#define ACC200_QOS_GBR 0
+#define VRBPF_DRIVER_NAME ("intel_vran_boost_pf")
+#define VRBVF_DRIVER_NAME ("intel_vran_boost_vf")
+#define VRB_QMGR_NUM_AQS 16
+#define VRB_QMGR_NUM_QGS 2
+#define VRB_QMGR_AQ_DEPTH 5
+#define VRB_QMGR_INVALID_IDX -1
+#define VRB_QMGR_RR 1
+#define VRB_QOS_GBR 0
#endif
#define OPS_CACHE_SIZE 256U
@@ -794,11 +794,11 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,
info->dev_name);
}
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME))) {
+ (!strcmp(info->drv.driver_name, VRBPF_DRIVER_NAME))) {
struct rte_acc_conf conf;
unsigned int i;
- printf("Configure ACC200 FEC Driver %s with default values\n",
+ printf("Configure Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -807,52 +807,51 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,
/* Always set in PF mode for built-in configuration */
conf.pf_mode_en = true;
for (i = 0; i < RTE_ACC_NUM_VFS; ++i) {
- conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_dl_4g[i].round_robin_weight = ACC200_QMGR_RR;
- conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_ul_4g[i].round_robin_weight = ACC200_QMGR_RR;
- conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_dl_5g[i].round_robin_weight = ACC200_QMGR_RR;
- conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_ul_5g[i].round_robin_weight = ACC200_QMGR_RR;
- conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
- conf.arb_fft[i].round_robin_weight = ACC200_QMGR_RR;
+ conf.arb_dl_4g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_dl_4g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_dl_4g[i].round_robin_weight = VRB_QMGR_RR;
+ conf.arb_ul_4g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_ul_4g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_ul_4g[i].round_robin_weight = VRB_QMGR_RR;
+ conf.arb_dl_5g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_dl_5g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_dl_5g[i].round_robin_weight = VRB_QMGR_RR;
+ conf.arb_ul_5g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_ul_5g[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_ul_5g[i].round_robin_weight = VRB_QMGR_RR;
+ conf.arb_fft[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_fft[i].gbr_threshold1 = VRB_QOS_GBR;
+ conf.arb_fft[i].round_robin_weight = VRB_QMGR_RR;
}
conf.input_pos_llr_1_bit = true;
conf.output_pos_llr_1_bit = true;
conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
- conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
- conf.q_ul_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
- conf.q_ul_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
- conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
- conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
- conf.q_dl_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
- conf.q_dl_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
- conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
- conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
- conf.q_ul_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
- conf.q_ul_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
- conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
- conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
- conf.q_dl_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
- conf.q_dl_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
- conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
- conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;
- conf.q_fft.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
- conf.q_fft.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
- conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+ conf.q_ul_4g.num_qgroups = VRB_QMGR_NUM_QGS;
+ conf.q_ul_4g.first_qgroup_index = VRB_QMGR_INVALID_IDX;
+ conf.q_ul_4g.num_aqs_per_groups = VRB_QMGR_NUM_AQS;
+ conf.q_ul_4g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH;
+ conf.q_dl_4g.num_qgroups = VRB_QMGR_NUM_QGS;
+ conf.q_dl_4g.first_qgroup_index = VRB_QMGR_INVALID_IDX;
+ conf.q_dl_4g.num_aqs_per_groups = VRB_QMGR_NUM_AQS;
+ conf.q_dl_4g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH;
+ conf.q_ul_5g.num_qgroups = VRB_QMGR_NUM_QGS;
+ conf.q_ul_5g.first_qgroup_index = VRB_QMGR_INVALID_IDX;
+ conf.q_ul_5g.num_aqs_per_groups = VRB_QMGR_NUM_AQS;
+ conf.q_ul_5g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH;
+ conf.q_dl_5g.num_qgroups = VRB_QMGR_NUM_QGS;
+ conf.q_dl_5g.first_qgroup_index = VRB_QMGR_INVALID_IDX;
+ conf.q_dl_5g.num_aqs_per_groups = VRB_QMGR_NUM_AQS;
+ conf.q_dl_5g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH;
+ conf.q_fft.num_qgroups = VRB_QMGR_NUM_QGS;
+ conf.q_fft.first_qgroup_index = VRB_QMGR_INVALID_IDX;
+ conf.q_fft.num_aqs_per_groups = VRB_QMGR_NUM_AQS;
/* setup PF with configuration information */
ret = rte_acc_configure(info->dev_name, &conf);
TEST_ASSERT_SUCCESS(ret,
- "Failed to configure ACC200 PF for bbdev %s",
+ "Failed to configure PF for bbdev %s",
info->dev_name);
}
#endif
--
2.37.1
next prev parent reply other threads:[~2023-09-29 20:15 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 18:13 [PATCH v1 00/11] test-bbdev changes for 23.11 Hernan Vargas
2023-09-29 18:13 ` [PATCH v1 01/11] test/bbdev: fix python script subprocess Hernan Vargas
2023-10-17 19:05 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 02/11] test/bbdev: update python script parameters Hernan Vargas
2023-10-17 19:07 ` Maxime Coquelin
2023-10-19 9:01 ` Chautru, Nicolas
2023-10-19 9:19 ` Maxime Coquelin
2023-10-19 12:09 ` Chautru, Nicolas
2023-10-19 12:20 ` Maxime Coquelin
2023-10-27 20:02 ` Chautru, Nicolas
2023-11-02 17:00 ` Maxime Coquelin
2023-11-02 18:18 ` Chautru, Nicolas
2023-11-03 9:48 ` Maxime Coquelin
2023-09-29 18:13 ` Hernan Vargas [this message]
2023-10-17 19:30 ` [PATCH v1 03/11] test/bbdev: rename macros from acc200 to vrb Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 04/11] test/bbdev: handle exception for LLR generation Hernan Vargas
2023-10-17 19:30 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 05/11] test/bbdev: improve test log messages Hernan Vargas
2023-10-17 19:40 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 06/11] test/bbdev: assert failed test for queue configure Hernan Vargas
2023-10-17 19:43 ` Maxime Coquelin
2023-10-19 8:41 ` Chautru, Nicolas
2023-10-19 8:47 ` Maxime Coquelin
2023-10-19 12:12 ` Chautru, Nicolas
2023-10-23 9:05 ` Maxime Coquelin
2023-10-23 9:07 ` Maxime Coquelin
2023-10-23 15:10 ` Kevin Traynor
2023-09-29 18:13 ` [PATCH v1 07/11] test/bbdev: ldpc encoder concatenation vector Hernan Vargas
2023-10-17 19:44 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 08/11] test/bbdev: increase max burst size Hernan Vargas
2023-10-17 19:45 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 09/11] test/bbdev: add MLD support Hernan Vargas
2023-10-17 20:03 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 10/11] test/bbdev: support new FFT capabilities Hernan Vargas
2023-10-17 20:06 ` Maxime Coquelin
2023-09-29 18:13 ` [PATCH v1 11/11] test/bbdev: support 4 bit LLR compression Hernan Vargas
2023-10-17 20:08 ` Maxime Coquelin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230929181328.104311-4-hernan.vargas@intel.com \
--to=hernan.vargas@intel.com \
--cc=dev@dpdk.org \
--cc=gakhil@marvell.com \
--cc=maxime.coquelin@redhat.com \
--cc=nicolas.chautru@intel.com \
--cc=qi.z.zhang@intel.com \
--cc=trix@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).