From: Abdullah Sevincer <abdullah.sevincer@intel.com>
To: dev@dpdk.org
Cc: jerinj@marvell.com, mike.ximing.chen@intel.com,
bruce.richardson@intel.com, thomas@monjalon.net,
Abdullah Sevincer <abdullah.sevincer@intel.com>,
stable@dpdk.org
Subject: [PATCH v5 2/2] event/dlb2: fix disable PASID
Date: Fri, 3 Nov 2023 12:52:04 -0500 [thread overview]
Message-ID: <20231103175204.2812654-3-abdullah.sevincer@intel.com> (raw)
In-Reply-To: <20231103175204.2812654-1-abdullah.sevincer@intel.com>
In vfio-pci driver when PASID is enabled by default DLB hardware puts
DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to
function properly PASID needs to be disabled.
In this commit this issue is addressed and PASID is disabled by writing
a zero to PASID control register.
Fixes: 5433956d5185 ("event/dlb2: add eventdev probe")
Cc: stable@dpdk.org
Signed-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
---
drivers/event/dlb2/pf/dlb2_main.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c
index aa03e4c311..843fe215aa 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -514,6 +514,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
}
}
+ /* Disable PASID if it is enabled by default, which
+ * breaks the DLB if enabled.
+ */
+ off = RTE_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL;
+ if (rte_pci_set_pasid(pdev, off, false)) {
+ DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n",
+ __func__, (int)off);
+ return -1;
+ }
+
return 0;
}
--
2.25.1
parent reply other threads:[~2023-11-03 17:53 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20231103175204.2812654-1-abdullah.sevincer@intel.com>]
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