From: Venkat Kumar Ande <venkatkumar.ande@amd.com>
To: <dev@dpdk.org>
Cc: <Selwin.Sebastian@amd.com>,
Venkat Kumar Ande <venkatkumar.ande@amd.com>, <stable@dpdk.org>
Subject: [PATCH v2 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs
Date: Tue, 7 May 2024 18:12:41 +0530 [thread overview]
Message-ID: <20240507124305.2318-1-venkatkumar.ande@amd.com> (raw)
In-Reply-To: <20240412125013.10498-1-VenkatKumar.Ande@amd.com>
The XGBE supports performing MDIO operations using an MDIO command
request. The driver mistakenly uses the mdio port address as the
MDIO command request device address instead of the MDIO command
request port address. Additionally, the driver does not properly check
for and create a clause 45 MDIO command
Without the fix user will get a incorrect value from PHY device.
Check the supplied MDIO register to determine if the request is a clause
45 operation (MII_ADDR_C45). For a clause 45 operation, extract device
address and register number from the supplied MDIO register and use them
to set the MDIO command request device address and register number fields.
For a clause 22 operation, the MDIO request device address is set to zero
and the MDIO command request register number is set to the supplied MDIO
register. In either case, the supplied MDIO port address is used as the
MDIO command request port address.
Fixes: 4ac7516b8b39 ("net/axgbe: add phy init and related APIs")
Cc: stable@dpdk.org
Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 2 --
drivers/net/axgbe/axgbe_dev.c | 22 ++++++++++++++++------
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5d11c5832..51532fb34a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -407,8 +407,6 @@
#define MAC_MDIOSCAR_PA_WIDTH 5
#define MAC_MDIOSCAR_RA_INDEX 0
#define MAC_MDIOSCAR_RA_WIDTH 16
-#define MAC_MDIOSCAR_REG_INDEX 0
-#define MAC_MDIOSCAR_REG_WIDTH 21
#define MAC_MDIOSCCDR_BUSY_INDEX 22
#define MAC_MDIOSCCDR_BUSY_WIDTH 1
#define MAC_MDIOSCCDR_CMD_INDEX 16
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 6a7fddffca..3389954aa6 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -63,15 +63,27 @@ static int mdio_complete(struct axgbe_port *pdata)
return 0;
}
+static unsigned int axgbe_create_mdio_sca(int port, int reg)
+{
+ unsigned int mdio_sca, da;
+
+ da = (reg & MII_ADDR_C45) ? reg >> 16 : 0;
+
+ mdio_sca = 0;
+ AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
+ AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port);
+ AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da);
+
+ return mdio_sca;
+}
+
static int axgbe_write_ext_mii_regs(struct axgbe_port *pdata, int addr,
int reg, u16 val)
{
unsigned int mdio_sca, mdio_sccd;
uint64_t timeout;
- mdio_sca = 0;
- AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
- AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
+ mdio_sca = axgbe_create_mdio_sca(addr, reg);
AXGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
mdio_sccd = 0;
@@ -97,9 +109,7 @@ static int axgbe_read_ext_mii_regs(struct axgbe_port *pdata, int addr,
unsigned int mdio_sca, mdio_sccd;
uint64_t timeout;
- mdio_sca = 0;
- AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
- AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
+ mdio_sca = axgbe_create_mdio_sca(addr, reg);
AXGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
mdio_sccd = 0;
--
2.34.1
next parent reply other threads:[~2024-05-07 12:43 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240412125013.10498-1-VenkatKumar.Ande@amd.com>
2024-05-07 12:42 ` Venkat Kumar Ande [this message]
2024-05-07 12:42 ` [PATCH v2 02/25] net/axgbe: reset link when the link never comes back Venkat Kumar Ande
2024-05-20 10:40 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 03/25] net/axgbe: fix fluctuations for 1G BELFUSE SFP Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 04/25] net/axgbe: update DMA coherency values Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 05/25] net/axgbe: disable interrupts during device removal Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 06/25] net/axgbe: yellow carp devices do not need rrc Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 07/25] net/axgbe: enable PLL control for fixed PHY modes only Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-20 11:25 ` Ferruh Yigit
2024-05-07 12:42 ` [PATCH v2 08/25] net/axgbe: fix the SFP codes check for DAC cables Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 09/25] net/axgbe: fix logic around active and passive cables Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 10/25] net/axgbe: check only the minimum speed for cables Venkat Kumar Ande
2024-05-20 10:42 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 11/25] net/axgbe: flow Tx Ctrl Registers are h/w version dependent Venkat Kumar Ande
2024-05-20 10:42 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 12/25] net/axgbe: delay AN timeout during KR training Venkat Kumar Ande
2024-05-20 10:42 ` Sebastian, Selwin
2024-05-07 12:43 ` [PATCH v2 23/25] net/axgbe: fix the false linkup in axgbe PHY status Venkat Kumar Ande
2024-05-20 10:43 ` Sebastian, Selwin
2024-05-20 11:25 ` Ferruh Yigit
2024-05-20 10:40 ` [PATCH v2 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Sebastian, Selwin
2024-05-20 11:26 ` Ferruh Yigit
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