From: Venkat Kumar Ande <venkatkumar.ande@amd.com>
To: <dev@dpdk.org>
Cc: <Selwin.Sebastian@amd.com>,
Venkat Kumar Ande <venkatkumar.ande@amd.com>, <stable@dpdk.org>
Subject: [PATCH v2 12/25] net/axgbe: delay AN timeout during KR training
Date: Tue, 7 May 2024 18:12:52 +0530 [thread overview]
Message-ID: <20240507124305.2318-12-venkatkumar.ande@amd.com> (raw)
In-Reply-To: <20240507124305.2318-1-venkatkumar.ande@amd.com>
AN restart triggered during KR training not only aborts the KR training
process but also move the HW to unstable state. Driver has to wait up to
500ms or until the KR training is completed before restarting AN cycle.
Without the fix the user will face KR training failure issues.
Fixes: a5c7273771e8 ("net/axgbe: add phy programming APIs")
Cc: stable@dpdk.org
Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
---
drivers/net/axgbe/axgbe_ethdev.h | 2 ++
drivers/net/axgbe/axgbe_mdio.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index f122dfd516..d1fac667c2 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -111,6 +111,7 @@
/* Auto-negotiation */
#define AXGBE_AN_MS_TIMEOUT 500
#define AXGBE_LINK_TIMEOUT 5
+#define AXGBE_KR_TRAINING_WAIT_ITER 50
#define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
#define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
@@ -661,6 +662,7 @@ struct axgbe_port {
unsigned int parallel_detect;
unsigned int fec_ability;
unsigned long an_start;
+ unsigned long kr_start_time;
enum axgbe_an_mode an_mode;
/* I2C support */
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c
index b03bc471cb..e1a737cf62 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -357,6 +357,7 @@ static enum axgbe_an axgbe_an73_tx_training(struct axgbe_port *pdata,
reg |= AXGBE_KR_TRAINING_ENABLE;
reg |= AXGBE_KR_TRAINING_START;
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+ pdata->kr_start_time = rte_get_timer_cycles();
PMD_DRV_LOG(DEBUG, "KR training initiated\n");
if (pdata->phy_if.phy_impl.kr_training_post)
@@ -487,6 +488,7 @@ static enum axgbe_an axgbe_an73_incompat_link(struct axgbe_port *pdata)
axgbe_an_disable(pdata);
axgbe_switch_mode(pdata);
+ pdata->an_result = AXGBE_AN_READY;
axgbe_an_restart(pdata);
return AXGBE_AN_INCOMPAT_LINK;
@@ -967,11 +969,34 @@ static void axgbe_check_link_timeout(struct axgbe_port *pdata)
{
unsigned long link_timeout;
unsigned long ticks;
+ unsigned long kr_time;
+ int wait;
link_timeout = pdata->link_check + (AXGBE_LINK_TIMEOUT *
2 * rte_get_timer_hz());
ticks = rte_get_timer_cycles();
if (time_after(ticks, link_timeout)) {
+ if ((axgbe_cur_mode(pdata) == AXGBE_MODE_KR) &&
+ pdata->phy.autoneg == AUTONEG_ENABLE) {
+ /* AN restart should not happen while KR training is in progress.
+ * The while loop ensures no AN restart during KR training,
+ * waits up to 500ms and AN restart is triggered only if KR
+ * training is failed.
+ */
+ wait = AXGBE_KR_TRAINING_WAIT_ITER;
+ while (wait--) {
+ kr_time = pdata->kr_start_time +
+ msecs_to_timer_cycles(AXGBE_AN_MS_TIMEOUT);
+ ticks = rte_get_timer_cycles();
+ if (time_after(ticks, kr_time))
+ break;
+ /* AN restart is not required, if AN result is COMPLETE */
+ if (pdata->an_result == AXGBE_AN_COMPLETE)
+ return;
+ rte_delay_us(10500);
+ }
+ }
+
PMD_DRV_LOG(NOTICE, "AN link timeout\n");
axgbe_phy_config_aneg(pdata);
}
--
2.34.1
next prev parent reply other threads:[~2024-05-07 12:44 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240412125013.10498-1-VenkatKumar.Ande@amd.com>
2024-05-07 12:42 ` [PATCH v2 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Venkat Kumar Ande
2024-05-07 12:42 ` [PATCH v2 02/25] net/axgbe: reset link when the link never comes back Venkat Kumar Ande
2024-05-20 10:40 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 03/25] net/axgbe: fix fluctuations for 1G BELFUSE SFP Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 04/25] net/axgbe: update DMA coherency values Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 05/25] net/axgbe: disable interrupts during device removal Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 06/25] net/axgbe: yellow carp devices do not need rrc Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 07/25] net/axgbe: enable PLL control for fixed PHY modes only Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-20 11:25 ` Ferruh Yigit
2024-05-07 12:42 ` [PATCH v2 08/25] net/axgbe: fix the SFP codes check for DAC cables Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 09/25] net/axgbe: fix logic around active and passive cables Venkat Kumar Ande
2024-05-20 10:41 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 10/25] net/axgbe: check only the minimum speed for cables Venkat Kumar Ande
2024-05-20 10:42 ` Sebastian, Selwin
2024-05-07 12:42 ` [PATCH v2 11/25] net/axgbe: flow Tx Ctrl Registers are h/w version dependent Venkat Kumar Ande
2024-05-20 10:42 ` Sebastian, Selwin
2024-05-07 12:42 ` Venkat Kumar Ande [this message]
2024-05-20 10:42 ` [PATCH v2 12/25] net/axgbe: delay AN timeout during KR training Sebastian, Selwin
2024-05-07 12:43 ` [PATCH v2 23/25] net/axgbe: fix the false linkup in axgbe PHY status Venkat Kumar Ande
2024-05-20 10:43 ` Sebastian, Selwin
2024-05-20 11:25 ` Ferruh Yigit
2024-05-20 10:40 ` [PATCH v2 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Sebastian, Selwin
2024-05-20 11:26 ` Ferruh Yigit
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