From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Hernan Vargas <hernan.vargas@intel.com>,
dev@dpdk.org, gakhil@marvell.com, trix@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com
Subject: Re: [PATCH v2 15/37] baseband/acc100: add workaround for deRM corner cases
Date: Thu, 15 Sep 2022 10:15:18 +0200 [thread overview]
Message-ID: <20a46f14-e564-bab4-da88-6eeefcb9a1d0@redhat.com> (raw)
In-Reply-To: <20220820023157.189047-16-hernan.vargas@intel.com>
On 8/20/22 04:31, Hernan Vargas wrote:
> Add function to asses if de-ratematch pre-processing should be run
> in SW for corner cases.
>
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
> drivers/baseband/acc100/acc100_pmd.h | 13 +++
> drivers/baseband/acc100/rte_acc100_pmd.c | 103 ++++++++++++++++++++++-
> 2 files changed, 114 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h
> index 19a1f434bc..c98a182be6 100644
> --- a/drivers/baseband/acc100/acc100_pmd.h
> +++ b/drivers/baseband/acc100/acc100_pmd.h
> @@ -140,6 +140,8 @@
> /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
> #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
> #define ACC100_N_ZC_2 50 /* N = 50 Zc for BG 2 */
> +#define ACC100_K_ZC_1 22 /* K = 22 Zc for BG 1 */
> +#define ACC100_K_ZC_2 10 /* K = 10 Zc for BG 2 */
> #define ACC100_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
> #define ACC100_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
> #define ACC100_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
> @@ -177,6 +179,16 @@
> #define ACC100_MS_IN_US (1000)
> #define ACC100_DDR_TRAINING_MAX (5000)
>
> +/* Code rate limitation when padding is required */
> +#define ACC100_LIM_03 2 /* 0.03 */
> +#define ACC100_LIM_09 6 /* 0.09 */
> +#define ACC100_LIM_14 9 /* 0.14 */
> +#define ACC100_LIM_21 14 /* 0.21 */
> +#define ACC100_LIM_31 20 /* 0.31 */
> +#define ACC100_MAX_E (128 * 1024 - 2)
> +
> +
> +
> /* ACC100 DMA Descriptor triplet */
> struct acc100_dma_triplet {
> uint64_t address;
> @@ -572,6 +584,7 @@ struct __rte_cache_aligned acc100_queue {
> uint8_t *lb_out;
> rte_iova_t lb_in_addr_iova;
> rte_iova_t lb_out_addr_iova;
> + int8_t *derm_buffer; /* interim buffer for de-rm in SDK */
> struct acc100_device *d;
> };
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 1504acfadd..69c0714a37 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -24,6 +24,10 @@
> #include "acc100_pmd.h"
> #include "acc101_pmd.h"
>
> +#ifdef RTE_BBDEV_SDK_AVX512
> +#include <phy_rate_dematching_5gnr.h>
> +#endif
> +
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
> #else
> @@ -898,6 +902,16 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
> rte_free(q);
> return -ENOMEM;
> }
> + q->derm_buffer = rte_zmalloc_socket(dev->device->driver->name,
> + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10,
> + RTE_CACHE_LINE_SIZE, conf->socket);
> + if (q->derm_buffer == NULL) {
> + rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory");
> + rte_free(q->lb_in);
> + rte_free(q->lb_out);
> + rte_free(q);
> + return -ENOMEM;
> + }
It may make sense to have a common error path to avoid duplication and
so risk introducing memory leaks when changes will be made.
> q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out);
>
> /*
> @@ -918,6 +932,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
>
> q_idx = acc100_find_free_queue_idx(dev, conf);
> if (q_idx == -1) {
> + rte_free(q->derm_buffer);
> rte_free(q->lb_in);
> rte_free(q->lb_out);
> rte_free(q);
> @@ -955,6 +970,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id)
> /* Mark the Queue as un-assigned */
> d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFF -
> (1 << q->aq_id));
> + rte_free(q->derm_buffer);
> rte_free(q->lb_in);
> rte_free(q->lb_out);
> rte_free(q);
> @@ -3512,10 +3528,42 @@ harq_loopback(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
> return 1;
> }
>
> +/** Assess whether a work around is required for the deRM corner cases */
> +static inline bool
> +derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc100_queue *q)
> +{
> + if (!is_acc100(q))
> + return false;
> + int32_t e = ldpc_dec->cb_params.e;
> + int q_m = ldpc_dec->q_m;
> + int z_c = ldpc_dec->z_c;
> + int K = (ldpc_dec->basegraph == 1 ? ACC100_K_ZC_1 : ACC100_K_ZC_2)
> + * z_c;
> + bool required = false;
Add new line.
> + if (ldpc_dec->basegraph == 1) {
> + if ((q_m == 4) && (z_c >= 320) && (e * ACC100_LIM_31 > K * 64))
> + required = true;
> + else if ((e * ACC100_LIM_21 > K * 64))
> + required = true;
> + } else {
> + if (q_m <= 2) {
> + if ((z_c >= 208) && (e * ACC100_LIM_09 > K * 64))
> + required = true;
> + else if ((z_c < 208) && (e * ACC100_LIM_03 > K * 64))
> + required = true;
> + } else if (e * ACC100_LIM_14 > K * 64)
> + required = true;
> + }
> + if (required)
> + rte_bbdev_log(INFO, "Running deRM pre-processing in SW");
Add new line.
> + return required;
> +}
> +
> /** Enqueue one decode operations for ACC100 device in CB mode */
> static inline int
> enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
> - uint16_t total_enqueued_cbs, bool same_op)
> + uint16_t total_enqueued_cbs, bool same_op,
> + struct rte_bbdev_queue_data *q_data)
> {
> int ret;
> if (unlikely(check_bit(op->ldpc_dec.op_flags,
> @@ -3571,6 +3619,57 @@ enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
> &in_offset, &h_out_offset,
> &h_out_length, harq_layout);
> } else {
> + if (derm_workaround_required(&op->ldpc_dec, q)) {
> + #ifdef RTE_BBDEV_SDK_AVX512
First, the indentation is not good here.
Also, my understanding is that this code will get built only if Flexran
SDK is available. Flexran SDK is proprietary, and so it is not possible
to have this code exercised by the upstream CI.
Code under RTE_BBDEV_SDK_AVX512 should be dropped IMO.
> + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
> + /* Checking input size is matching with E */
> + if (dec->input.data->data_len < dec->cb_params.e) {
> + rte_bbdev_log(ERR,
> + "deRM: Input size mismatch");
> + return -EFAULT;
> + }
> + /* Run first deRM processing in SW */
> + struct bblib_rate_dematching_5gnr_request derm_req;
> + struct bblib_rate_dematching_5gnr_response derm_resp;
> + uint8_t *in = rte_pktmbuf_mtod_offset(dec->input.data,
> + uint8_t *, in_offset);
Don't mix declarations & code.
> + derm_req.p_in = (int8_t *) in;
> + derm_req.p_harq = (int8_t *) q->derm_buffer;
> + derm_req.base_graph = dec->basegraph;
> + derm_req.zc = dec->z_c;
> + derm_req.ncb = dec->n_cb;
> + derm_req.e = dec->cb_params.e;
> + if (derm_req.e > ACC100_MAX_E) {
> + rte_bbdev_log(WARNING,
> + "deRM: E %d > %d max",
> + derm_req.e, ACC100_MAX_E);
> + derm_req.e = ACC100_MAX_E;
> + }
> + derm_req.k0 = 0; /* Actual output from SDK */
> + derm_req.isretx = false;
> + derm_req.rvid = dec->rv_index;
> + derm_req.modulation_order = dec->q_m;
> + derm_req.start_null_index =
> + (dec->basegraph == 1 ? 22 : 10)
> + * dec->z_c - 2 * dec->z_c
> + - dec->n_filler;
> + derm_req.num_of_null = dec->n_filler;
> + bblib_rate_dematching_5gnr(&derm_req, &derm_resp);
> + /* Force back the HW DeRM */
> + dec->q_m = 1;
> + dec->cb_params.e = dec->n_cb - dec->n_filler;
> + dec->rv_index = 0;
> + rte_memcpy(in, q->derm_buffer, dec->cb_params.e);
> + /* Capture counter when pre-processing is used */
> + q_data->queue_stats.enqueue_warn_count++;
> + #else
> + RTE_SET_USED(q_data);
> + rte_bbdev_log(WARNING,
> + "Corner case may require deRM pre-processing in SDK"
> + );
> + #endif
> + }
> +
> struct acc100_fcw_ld *fcw;
> uint32_t seg_total_left;
Don't mix declarations & code.
> fcw = &desc->req.fcw_ld;
> @@ -4322,7 +4421,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,
> ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m,
> ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e,
> same_op);
> - ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op);
> + ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data);
> if (ret < 0) {
> acc100_enqueue_invalid(q_data);
> break;
next prev parent reply other threads:[~2022-09-15 8:15 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-20 2:31 [PATCH v2 00/37] baseband/acc100: changes for 22.11 Hernan Vargas
2022-08-20 2:31 ` [PATCH v2 01/37] baseband/acc100: add enqueue status Hernan Vargas
2022-09-14 16:26 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 02/37] baseband/acc100: update ring availability calculation Hernan Vargas
2022-09-14 16:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 03/37] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-09-14 17:00 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 04/37] baseband/acc100: free SW ring mem for reconfiguration Hernan Vargas
2022-09-14 19:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 05/37] baseband/acc100: memory leak fix Hernan Vargas
2022-09-14 8:50 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 06/37] baseband/acc100: add default e value for FCW Hernan Vargas
2022-09-14 19:24 ` Maxime Coquelin
2022-09-15 11:00 ` Thomas Monjalon
2022-09-16 1:12 ` Chautru, Nicolas
2022-09-16 7:11 ` Thomas Monjalon
2022-08-20 2:31 ` [PATCH v2 07/37] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-09-14 19:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 08/37] baseband/acc100: add scatter-gather support Hernan Vargas
2022-09-14 20:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 09/37] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-09-14 20:16 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 10/37] baseband/acc100: avoid mux for small inbound frames Hernan Vargas
2022-09-14 20:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 11/37] baseband/acc100: separate validation functions from debug Hernan Vargas
2022-09-14 20:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 12/37] baseband/acc100: add LDPC transport block support Hernan Vargas
2022-09-14 20:47 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning Hernan Vargas
2022-09-15 7:37 ` Maxime Coquelin
2022-09-16 0:31 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 14/37] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-09-15 7:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 15/37] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-09-15 8:15 ` Maxime Coquelin [this message]
2022-09-16 1:20 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 16/37] baseband/acc100: add ring companion address Hernan Vargas
2022-09-15 9:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 17/37] baseband/acc100: configure PMON control registers Hernan Vargas
2022-09-15 9:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 18/37] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-09-15 9:52 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 19/37] baseband/acc100: add queue stop operation Hernan Vargas
2022-09-15 9:55 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 20/37] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-09-15 10:01 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 21/37] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-09-15 10:02 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 23/37] baseband/acc100: update uplink CB input length Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 24/37] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 25/37] baseband/acc100: update log messages Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 26/37] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-09-15 10:15 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 27/37] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-09-15 10:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 28/37] baseband/acc100: make desc optimization optional Hernan Vargas
2022-09-15 10:19 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 29/37] baseband/acc100: update device info Hernan Vargas
2022-09-15 10:20 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 30/37] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-09-15 10:21 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 31/37] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-09-15 10:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 32/37] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-09-15 10:23 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 33/37] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-09-15 10:24 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 34/37] baseband/acc100: update meson file sdk dependency Hernan Vargas
2022-09-15 10:31 ` Maxime Coquelin
2022-09-15 10:57 ` Thomas Monjalon
2022-09-16 0:39 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 35/37] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 36/37] baseband/acc100: make HARQ layout memory 4GB Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 37/37] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-09-15 11:34 ` Maxime Coquelin
2022-08-23 15:59 ` [EXT] [PATCH v2 00/37] baseband/acc100: changes for 22.11 Akhil Goyal
2022-08-24 18:23 ` Chautru, Nicolas
2022-09-06 20:03 ` Chautru, Nicolas
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