From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Jia He <hejianet@gmail.com>,
"jerin.jacob@caviumnetworks.com" <jerin.jacob@caviumnetworks.com>,
"dev@dpdk.org" <dev@dpdk.org>,
"olivier.matz@6wind.com" <olivier.matz@6wind.com>
Cc: "Richardson, Bruce" <bruce.richardson@intel.com>,
"jianbo.liu@arm.com" <jianbo.liu@arm.com>,
"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
"Jia He" <jia.he@hxt-semitech.com>,
"jie2.liu@hxt-semitech.com" <jie2.liu@hxt-semitech.com>,
"bing.zhao@hxt-semitech.com" <bing.zhao@hxt-semitech.com>
Subject: Re: [dpdk-dev] [PATCH v5 1/1] ring: guarantee load/load order in enqueue and dequeue
Date: Fri, 10 Nov 2017 09:59:13 +0000 [thread overview]
Message-ID: <2601191342CEEE43887BDE71AB9772585FABBC02@irsmsx105.ger.corp.intel.com> (raw)
In-Reply-To: <1510278669-8489-2-git-send-email-hejianet@gmail.com>
> -----Original Message-----
> From: Jia He [mailto:hejianet@gmail.com]
> Sent: Friday, November 10, 2017 1:51 AM
> To: jerin.jacob@caviumnetworks.com; dev@dpdk.org; olivier.matz@6wind.com
> Cc: Ananyev, Konstantin <konstantin.ananyev@intel.com>; Richardson, Bruce <bruce.richardson@intel.com>; jianbo.liu@arm.com;
> hemant.agrawal@nxp.com; Jia He <hejianet@gmail.com>; Jia He <jia.he@hxt-semitech.com>; jie2.liu@hxt-semitech.com; bing.zhao@hxt-
> semitech.com
> Subject: [PATCH v5 1/1] ring: guarantee load/load order in enqueue and dequeue
>
> We watched a rte panic of mbuf_autotest in our qualcomm arm64 server.
> In __rte_ring_move_cons_head()
> ...
> do {
> /* Restore n as it may change every loop */
> n = max;
>
> *old_head = r->cons.head; //1st load
> const uint32_t prod_tail = r->prod.tail; //2nd load
>
> cpu1(producer) cpu2(consumer) cpu3(consumer)
> load r->prod.tail
> in enqueue:
> load r->cons.tail
> load r->prod.head
>
> store r->prod.tail
>
> load r->cons.head
> load r->prod.tail
> ...
> store r->cons.{head,tail}
> load r->cons.head
>
> In weak memory order architectures(powerpc,arm), the 2nd load might be
> reodered before the 1st load, that makes *entries is bigger than we
> wanted. This nasty reording messed enque/deque up. Then, r->cons.head
> will be bigger than prod_tail, then make *entries very big and the
> consumer will go forward incorrectly.
>
> After this patch, even with above context switches, the old cons.head
> will be recaculated after failure of rte_atomic32_cmpset. So no race
> conditions left.
>
> There is no such issue on X86, because X86 is strong memory order model.
> But rte_smp_rmb() doesn't have impact on runtime performance on X86, so
> keep the same code without architectures specific concerns.
>
> Signed-off-by: Jia He <jia.he@hxt-semitech.com>
> Signed-off-by: jie2.liu@hxt-semitech.com
> Signed-off-by: bing.zhao@hxt-semitech.com
> ---
> lib/librte_ring/rte_ring.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h
> index 5e9b3b7..3e8085a 100644
> --- a/lib/librte_ring/rte_ring.h
> +++ b/lib/librte_ring/rte_ring.h
> @@ -409,6 +409,11 @@ __rte_ring_move_prod_head(struct rte_ring *r, int is_sp,
> n = max;
>
> *old_head = r->prod.head;
> +
> + /* add rmb barrier to avoid load/load reorder in weak
> + * memory model. It is noop on x86 */
> + rte_smp_rmb();
> +
> const uint32_t cons_tail = r->cons.tail;
> /*
> * The subtraction is done between two unsigned 32bits value
> @@ -517,6 +522,11 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
> n = max;
>
> *old_head = r->cons.head;
> +
> + /* add rmb barrier to avoid load/load reorder in weak
> + * memory model. It is noop on x86 */
> + rte_smp_rmb();
> +
> const uint32_t prod_tail = r->prod.tail;
> /* The subtraction is done between two unsigned 32bits value
> * (the result is always modulo 32 bits even if we have
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> 2.7.4
next prev parent reply other threads:[~2017-11-10 9:59 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1510118764-29697-1-git-send-email-hejianet@gmail.com>
2017-11-08 9:54 ` [dpdk-dev] [PATCH v4 0/4] fix race condition in enqueue/dequeue because of cpu reorder Jia He
2017-11-08 9:54 ` [dpdk-dev] [PATCH v4 1/4] eal/arm64: remove the braces {} for dmb() and dsb() Jia He
2017-11-08 9:54 ` [dpdk-dev] [PATCH v4 2/4] ring: guarantee load/load order in enqueue and dequeue Jia He
2017-11-08 9:54 ` [dpdk-dev] [PATCH v4 3/4] ring: introduce new header file to include common functions Jia He
2017-11-08 9:54 ` [dpdk-dev] [PATCH v4 4/4] ring: introduce new header file to support C11 memory model Jia He
2017-11-08 12:15 ` [dpdk-dev] [PATCH v4 0/4] fix race condition in enqueue/dequeue because of cpu reorder Bruce Richardson
2017-11-08 15:11 ` Jia He
2017-11-08 16:29 ` Jerin Jacob
2017-11-08 18:36 ` Ananyev, Konstantin
[not found] ` <2459a535-920e-9ac5-2f46-1d1dd00e275b@gmail.com>
2017-11-24 9:24 ` Bruce Richardson
2017-11-10 1:51 ` [dpdk-dev] [PATCH v5 0/1] " Jia He
2017-11-10 1:51 ` [dpdk-dev] [PATCH v5 1/1] ring: guarantee load/load order in enqueue and dequeue Jia He
2017-11-10 2:46 ` Jerin Jacob
2017-11-10 3:12 ` Jianbo Liu
2017-11-10 9:59 ` Ananyev, Konstantin [this message]
2017-11-10 3:30 ` [dpdk-dev] [PATCH v6] " Jia He
2017-11-10 3:30 ` [dpdk-dev] [PATCH v6] ring: " Jia He
2017-11-12 17:51 ` [dpdk-dev] [dpdk-stable] " Thomas Monjalon
2017-11-10 5:23 ` [dpdk-dev] [PATCH v5 0/3] support c11 memory model barrier in librte_ring Jia He
2017-11-10 5:23 ` [dpdk-dev] [PATCH v5 1/3] eal/arm64: remove the braces {} for dmb() and dsb() Jia He
2017-11-10 5:23 ` [dpdk-dev] [PATCH v5 2/3] ring: introduce new header file to include common functions Jia He
2017-11-10 5:23 ` [dpdk-dev] [PATCH v6 3/3] ring: introduce new header file to support C11 memory model Jia He
2017-11-27 2:00 ` [dpdk-dev] [PATCH V6 0/3] support c11 memory model barrier in librte_ring Jia He
2017-11-27 2:00 ` [dpdk-dev] [PATCH V6 1/3] eal/arm64: remove the braces {} for dmb() and dsb() Jia He
2017-12-03 11:11 ` Jerin Jacob
2017-11-27 2:00 ` [dpdk-dev] [PATCH V6 2/3] ring: introduce new header file to include common functions Jia He
2017-12-03 12:13 ` Jerin Jacob
2017-11-27 2:00 ` [dpdk-dev] [PATCH V6 3/3] ring: introduce new header file to support C11 memory model Jia He
2017-12-03 12:14 ` Jerin Jacob
2017-12-04 1:50 ` [dpdk-dev] [PATCH V7 0/3] support c11 memory model barrier in librte_ring Jia He
2017-12-04 1:50 ` [dpdk-dev] [PATCH V7 1/3] eal/arm64: remove the braces {} for dmb() and dsb() Jia He
2017-12-04 1:50 ` [dpdk-dev] [PATCH V7 2/3] ring: introduce new header file to include common functions Jia He
2018-01-12 17:09 ` Thomas Monjalon
2018-01-16 2:06 ` Jia He
2018-01-16 15:19 ` Olivier Matz
2017-12-04 1:50 ` [dpdk-dev] [PATCH V7 3/3] ring: introduce new header file to support C11 memory model Jia He
2017-12-04 8:05 ` Jianbo Liu
2018-01-12 17:18 ` Thomas Monjalon
2018-01-16 15:18 ` Olivier Matz
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