From: Thomas Monjalon <thomas@monjalon.net>
To: Volodymyr Fialko <vfialko@marvell.com>
Cc: dev@dpdk.org, Reshma Pattan <reshma.pattan@intel.com>,
jerinj@marvell.com, anoobj@marvell.com,
bruce.richardson@intel.com, stephen@networkplumber.org,
roretzla@linux.microsoft.com
Subject: Re: [PATCH v2] reorder: improve buffer structure layout
Date: Thu, 01 Jun 2023 17:19:50 +0200 [thread overview]
Message-ID: <3165123.NnENhoQgcM@thomas> (raw)
In-Reply-To: <20230417091233.1406974-1-vfialko@marvell.com>
17/04/2023 11:12, Volodymyr Fialko:
> Rearrange the reorder buffer structure to prevent padding to extra one
> cache line.
>
> Current layout:
> struct rte_reorder_buffer {
> char name[RTE_REORDER_NAMESIZE];
> uint32_t min_seqn;
> unsigned int memsize;
> // -> padding to cache align (cir_buffer is also cache aligned)
> struct cir_buffer ready_buf;
> struct cir_buffer order_buf;
> int is_initialized;
> // -> padding to cache align, eat whole line
> };
>
> New layout:
> struct rte_reorder_buffer {
> char name[RTE_REORDER_NAMESIZE];
> uint32_t min_seqn;
> unsigned int memsize;
> bool is_initialized;
> // -> padding to cache align (cir_buffer is also cache aligned)
> struct cir_buffer ready_buf;
> struct cir_buffer order_buf;
> // -> no padding
> };
>
> Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Applied, thanks.
prev parent reply other threads:[~2023-06-01 15:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-14 8:43 [PATCH] " Volodymyr Fialko
2023-04-14 9:26 ` Bruce Richardson
2023-04-14 17:07 ` Tyler Retzlaff
2023-04-14 14:52 ` Stephen Hemminger
2023-04-14 14:54 ` Bruce Richardson
2023-04-14 15:30 ` Stephen Hemminger
2023-04-17 9:12 ` [PATCH v2] " Volodymyr Fialko
2023-06-01 15:19 ` Thomas Monjalon [this message]
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