From: Linhaifeng <haifeng.lin@huawei.com>
To: David Marchand <david.marchand@redhat.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
"thomas@monjalon.net" <thomas@monjalon.net>,
"Lilijun (Jerry)" <jerry.lilijun@huawei.com>,
chenchanghu <chenchanghu@huawei.com>,
xudingke <xudingke@huawei.com>
Subject: [dpdk-dev] 答复: [PATCH] cycles: add isb before read cntvct_el0
Date: Tue, 10 Mar 2020 02:51:20 +0000 [thread overview]
Message-ID: <4099DE2E54AFAD489356C6C9161D53339729F33C@DGGEML502-MBX.china.huawei.com> (raw)
In-Reply-To: <CAJFAV8y1=a5HgxpX5Dv-CzSPV+0mviPUwH5GRHZKAV=5draEtg@mail.gmail.com>
-----邮件原件-----
发件人: David Marchand [mailto:david.marchand@redhat.com]
发送时间: 2020年3月9日 17:19
收件人: Linhaifeng <haifeng.lin@huawei.com>
抄送: dev@dpdk.org; thomas@monjalon.net; Lilijun (Jerry) <jerry.lilijun@huawei.com>; chenchanghu <chenchanghu@huawei.com>; xudingke <xudingke@huawei.com>
主题: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0
On Mon, Mar 9, 2020 at 10:14 AM Linhaifeng <haifeng.lin@huawei.com> wrote:
>
> We nead isb rather than dsb to sync system counter to cntvct_el0.
I'll leave the arm maintainers look at this, but I have a comment on the form.
Thank you
>
> Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
> ---
> lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++
> lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae129d..705351394 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -21,6 +21,7 @@ extern "C" {
>
> #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define
> dmb(opt) asm volatile("dmb " #opt : : : "memory")
> +#define isb() asm volatile("isb" : : : "memory")
dsb and dmb should not be exported as public macros in the first place (I forgot to send the patch that drops those, will send later).
Please don't add more public macro that make no sense except for
aarch64: neither isb, nor rte_isb.
Ok.I will send a new patch after yours.
>
> #define rte_mb() dsb(sy)
>
> @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
> return (old.int128 == expected.int128); }
>
> +#define rte_isb() isb()
> +
> #ifdef __cplusplus
> }
> #endif
--
David Marchand
next prev parent reply other threads:[~2020-03-10 2:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 9:13 [dpdk-dev] " Linhaifeng
2020-03-09 9:19 ` David Marchand
2020-03-10 2:51 ` Linhaifeng [this message]
2020-03-09 15:43 ` Jerin Jacob
2020-03-10 2:39 ` [dpdk-dev] 答复: " Linhaifeng
2020-03-10 7:53 ` [dpdk-dev] " Jerin Jacob
2020-03-09 9:22 Linhaifeng
2020-03-10 7:11 ` Gavin Hu
2020-03-10 7:22 ` Linhaifeng
2020-03-10 7:50 ` Jerin Jacob
2020-03-09 10:58 Linhaifeng
2020-03-09 11:05 Linhaifeng
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