From: "Dai, Wei" <wei.dai@intel.com>
To: "Lu, Wenzhuo" <wenzhuo.lu@intel.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Ma, Jianwei" <jianwei.ma@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, "stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-stable] [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF
Date: Tue, 10 Oct 2017 03:25:39 +0000 [thread overview]
Message-ID: <49759EB36A64CF4892C1AFEC9231E8D650B9FC8B@PGSMSX106.gar.corp.intel.com> (raw)
In-Reply-To: <1505902693-51337-1-git-send-email-wei.dai@intel.com>
Hi, Jianwei
How about your test result ?
Hi, Wenzhuo
Would you please review this patch ?
Thanks a lot !
> -----Original Message-----
> From: Dai, Wei
> Sent: Wednesday, September 20, 2017 6:18 PM
> To: Lu, Wenzhuo <wenzhuo.lu@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>
> Cc: dev@dpdk.org; Dai, Wei <wei.dai@intel.com>; stable@dpdk.org
> Subject: [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF
>
> When a VF port is bound to VFIO-PCI, miscellaneous interrupt is mapped to
> MSI-X vector 0 and Rx queues interrupt are mapped to other vectors in
> vfio_enable_msix( ). To simplify implementation, all VFIO-PCI bound ixgbe VF
> Rx queue interrupts can be mapped in vector 1. And as current igb_uio only
> support only one vector, ixgbe VF PMD should use vector 0 for igb_uio and
> vector 1 for VFIO-PCI. Without this patch, VF Rx queue interrupt is mapped
> to vector 0 in register settings and mapped to VFIO vector 1 in
> vfio_enable_msix( ), and then all Rx queue interrupts will be missed.
>
> Fixes: b13bfab4cdbe ("eal: reserve VFIO vector zero for misc interrupt")
> Cc: stable@dpdk.org
>
> Signed-off-by: Wei Dai <wei.dai@intel.com>
> ---
> drivers/net/ixgbe/ixgbe_ethdev.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c
> b/drivers/net/ixgbe/ixgbe_ethdev.c
> index 9ca5cbc..39a3d8c 100644
> --- a/drivers/net/ixgbe/ixgbe_ethdev.c
> +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
> @@ -5029,7 +5029,10 @@ ixgbevf_dev_start(struct rte_eth_dev *dev)
>
> /* check and configure queue intr-vector mapping */
> if (dev->data->dev_conf.intr_conf.rxq != 0) {
> - intr_vector = dev->data->nb_rx_queues;
> + /* According to datasheet, only vector 0/1/2 can be used,
> + * now only one vector is used for Rx queue
> + */
> + intr_vector = 1;
> if (rte_intr_efd_enable(intr_handle, intr_vector))
> return -1;
> }
> @@ -5556,9 +5559,12 @@ ixgbevf_dev_rx_queue_intr_enable(struct
> rte_eth_dev *dev, uint16_t queue_id)
> uint32_t mask;
> struct ixgbe_hw *hw =
> IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> + uint32_t vec = IXGBE_MISC_VEC_ID;
>
> mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
> - mask |= (1 << IXGBE_MISC_VEC_ID);
> + if (rte_intr_allow_others(intr_handle))
> + vec = IXGBE_RX_VEC_START;
> + mask |= (1 << vec);
> RTE_SET_USED(queue_id);
> IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
>
> @@ -5573,9 +5579,14 @@ ixgbevf_dev_rx_queue_intr_disable(struct
> rte_eth_dev *dev, uint16_t queue_id)
> uint32_t mask;
> struct ixgbe_hw *hw =
> IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
> + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
> + uint32_t vec = IXGBE_MISC_VEC_ID;
>
> mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
> - mask &= ~(1 << IXGBE_MISC_VEC_ID);
> + if (rte_intr_allow_others(intr_handle))
> + vec = IXGBE_RX_VEC_START;
> + mask &= ~(1 << vec);
> RTE_SET_USED(queue_id);
> IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
>
> @@ -5717,6 +5728,7 @@ ixgbevf_configure_msix(struct rte_eth_dev *dev)
> IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> uint32_t q_idx;
> uint32_t vector_idx = IXGBE_MISC_VEC_ID;
> + uint32_t base = IXGBE_MISC_VEC_ID;
>
> /* Configure VF other cause ivar */
> ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); @@ -5727,6 +5739,11
> @@ ixgbevf_configure_msix(struct rte_eth_dev *dev)
> if (!rte_intr_dp_is_en(intr_handle))
> return;
>
> + if (rte_intr_allow_others(intr_handle)) {
> + base = IXGBE_RX_VEC_START;
> + vector_idx = IXGBE_RX_VEC_START;
> + }
> +
> /* Configure all RX queues of VF */
> for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
> /* Force all queue use vector 0,
> @@ -5734,6 +5751,8 @@ ixgbevf_configure_msix(struct rte_eth_dev *dev)
> */
> ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
> intr_handle->intr_vec[q_idx] = vector_idx;
> + if (vector_idx < base + intr_handle->nb_efd - 1)
> + vector_idx++;
> }
> }
>
> --
> 2.7.5
next prev parent reply other threads:[~2017-10-10 3:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-20 10:18 Wei Dai
2017-10-10 3:25 ` Dai, Wei [this message]
[not found] ` <B90411854DEF0649BE56FC396188B4FC3B930B19@SHSMSX104.ccr.corp.intel.com>
2017-10-11 7:10 ` Dai, Wei
2017-10-11 3:13 ` Lu, Wenzhuo
2017-10-11 18:19 ` [dpdk-stable] [dpdk-dev] " Ferruh Yigit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=49759EB36A64CF4892C1AFEC9231E8D650B9FC8B@PGSMSX106.gar.corp.intel.com \
--to=wei.dai@intel.com \
--cc=dev@dpdk.org \
--cc=jianwei.ma@intel.com \
--cc=konstantin.ananyev@intel.com \
--cc=stable@dpdk.org \
--cc=wenzhuo.lu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).