From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Hernan Vargas <hernan.vargas@intel.com>,
dev@dpdk.org, gakhil@marvell.com, trix@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com
Subject: Re: [PATCH v2 17/37] baseband/acc100: configure PMON control registers
Date: Thu, 15 Sep 2022 11:12:58 +0200 [thread overview]
Message-ID: <593bc800-3db0-77fe-e3ef-2c32565a850a@redhat.com> (raw)
In-Reply-To: <20220820023157.189047-18-hernan.vargas@intel.com>
On 8/20/22 04:31, Hernan Vargas wrote:
> Adding back feature from ACC101.
> Expose the device status and add protection for corner cases.
> Enable performance monitor control registers.
>
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
> drivers/baseband/acc100/acc100_pf_enum.h | 52 +++++++++++++++++++++---
> drivers/baseband/acc100/acc100_pmd.h | 9 +++-
> drivers/baseband/acc100/acc100_vf_enum.h | 6 +++
> drivers/baseband/acc100/rte_acc100_pmd.c | 13 ++++++
> 4 files changed, 74 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
> index 2fba667627..d6a37a4147 100644
> --- a/drivers/baseband/acc100/acc100_pf_enum.h
> +++ b/drivers/baseband/acc100/acc100_pf_enum.h
> @@ -14,6 +14,7 @@
> enum {
> HWPfQmgrEgressQueuesTemplate = 0x0007FE00,
> HWPfQmgrIngressAq = 0x00080000,
> + HWPfAramStatus = 0x00810000,
> HWPfQmgrArbQAvail = 0x00A00010,
> HWPfQmgrArbQBlock = 0x00A00014,
> HWPfQmgrAqueueDropNotifEn = 0x00A00024,
> @@ -127,6 +128,9 @@ enum {
> HWPfDmaConfigUnexpComplDataEn = 0x00B808A8,
> HWPfDmaConfigUnexpComplDescrEn = 0x00B808AC,
> HWPfDmaConfigPtoutOutEn = 0x00B808B0,
> + HWPfDmaClusterHangCtrl = 0x00B80E00,
> + HWPfDmaClusterHangThld = 0x00B80E04,
> + HWPfDmaStopAxiThreshold = 0x00B80F3C,
> HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,
> HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,
> HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,
> @@ -328,11 +332,27 @@ enum {
> HwPfFecUl5g8IbDebugReg = 0x00BC8200,
> HwPfFecUl5g8ObLlrDebugReg = 0x00BC8204,
> HwPfFecUl5g8ObHarqDebugReg = 0x00BC8208,
> - HWPfFecDl5gCntrlReg = 0x00BCF000,
> - HWPfFecDl5gI2MThreshReg = 0x00BCF004,
> - HWPfFecDl5gVersionReg = 0x00BCF100,
> - HWPfFecDl5gFcwStatusReg = 0x00BCF104,
> - HWPfFecDl5gWarnReg = 0x00BCF108,
> + HwPfFecDl5g0CntrlReg = 0x00BCD000,
> + HwPfFecDl5g0I2MThreshReg = 0x00BCD004,
> + HwPfFecDl5g0VersionReg = 0x00BCD100,
> + HwPfFecDl5g0FcwStatusReg = 0x00BCD104,
> + HwPfFecDl5g0WarnReg = 0x00BCD108,
> + HwPfFecDl5g0IbDebugReg = 0x00BCD200,
> + HwPfFecDl5g0ObDebugReg = 0x00BCD204,
> + HwPfFecDl5g1CntrlReg = 0x00BCE000,
> + HwPfFecDl5g1I2MThreshReg = 0x00BCE004,
> + HwPfFecDl5g1VersionReg = 0x00BCE100,
> + HwPfFecDl5g1FcwStatusReg = 0x00BCE104,
> + HwPfFecDl5g1WarnReg = 0x00BCE108,
> + HwPfFecDl5g1IbDebugReg = 0x00BCE200,
> + HwPfFecDl5g1ObDebugReg = 0x00BCE204,
> + HwPfFecDl5g2CntrlReg = 0x00BCF000,
> + HwPfFecDl5g2I2MThreshReg = 0x00BCF004,
> + HwPfFecDl5g2VersionReg = 0x00BCF100,
> + HwPfFecDl5g2FcwStatusReg = 0x00BCF104,
> + HwPfFecDl5g2WarnReg = 0x00BCF108,
> + HwPfFecDl5g2IbDebugReg = 0x00BCF200,
> + HwPfFecDl5g2ObDebugReg = 0x00BCF204,
> HWPfFecUlVersionReg = 0x00BD0000,
> HWPfFecUlControlReg = 0x00BD0004,
> HWPfFecUlStatusReg = 0x00BD0008,
> @@ -345,6 +365,12 @@ enum {
> HWPfFecDlClusterStatusReg3 = 0x00BDF04C,
> HWPfFecDlClusterStatusReg4 = 0x00BDF050,
> HWPfFecDlClusterStatusReg5 = 0x00BDF054,
> + HwPfWbbThreshold = 0x00C20000,
> + HwPfWbbSpare = 0x00C20004,
> + HwPfWbbDebugCtl = 0x00C20010,
> + HwPfWbbDebug = 0x00C20014,
> + HwPfWbbError = 0x00C20020,
> + HwPfWbbErrorInjecti = 0x00C20024,
> HWPfChaFabPllPllrst = 0x00C40000,
> HWPfChaFabPllClk0 = 0x00C40004,
> HWPfChaFabPllClk1 = 0x00C40008,
> @@ -527,6 +553,10 @@ enum {
> HWPfHiDebugMemSnoopMsiFifo = 0x00C841F8,
> HWPfHiDebugMemSnoopInputFifo = 0x00C841FC,
> HWPfHiMsixMappingConfig = 0x00C84200,
> + HWPfHiErrInjectReg = 0x00C84204,
> + HWPfHiErrStatusReg = 0x00C84208,
> + HWPfHiErrMaskReg = 0x00C8420C,
> + HWPfHiErrFatalReg = 0x00C84210,
> HWPfHiJunkReg = 0x00C8FF00,
> HWPfDdrUmmcVer = 0x00D00000,
> HWPfDdrUmmcCap = 0x00D00010,
> @@ -545,6 +575,7 @@ enum {
> HWPfDdrMpcPbw2 = 0x00D00130,
> HWPfDdrMpcPbw1 = 0x00D00140,
> HWPfDdrMpcPbw0 = 0x00D00150,
> + HwPfDdrUmmcEccErrInj = 0x00D00190,
> HWPfDdrMemoryInit = 0x00D00200,
> HWPfDdrMemoryInitDone = 0x00D00210,
> HWPfDdrMemInitPhyTrng0 = 0x00D00240,
> @@ -876,6 +907,7 @@ enum {
> HwPfPcieSupFence = 0x00D8086C,
> HwPfPcieSupMtcs = 0x00D80870,
> HwPfPcieSupStatsum = 0x00D809B8,
> + HwPfPcieRomVersion = 0x00D80B0C,
> HwPfPciePcsDpStatus0 = 0x00D81000,
> HwPfPciePcsDpControl0 = 0x00D81004,
> HwPfPciePcsPmaStatusLane0 = 0x00D81008,
> @@ -1081,6 +1113,16 @@ enum {
> ACC100_PF_INT_QMGR_ERR = 13,
> ACC100_PF_INT_INT_REQ_OVERFLOW = 14,
> ACC100_PF_INT_APB_TIMEOUT = 15,
> + ACC100_PF_INT_CORE_HANG = 16,
> + ACC100_PF_INT_CLUSTER_HANG = 17,
> + ACC100_PF_INT_WBB_ERROR = 18,
> + ACC100_PF_INT_5G_EXTRAREAD = 24,
> + ACC100_PF_INT_5G_READ_TIMEOUT = 25,
> + ACC100_PF_INT_5G_ERROR = 26,
> + ACC100_PF_INT_PCIE_ERROR = 27,
> + ACC100_PF_INT_DDR_ERROR = 28,
> + ACC100_PF_INT_MISC_ERROR = 29,
> + ACC100_PF_INT_I2C = 30,
> };
>
> #endif /* ACC100_PF_ENUM_H */
> diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h
> index 20157e5886..27801767b7 100644
> --- a/drivers/baseband/acc100/acc100_pmd.h
> +++ b/drivers/baseband/acc100/acc100_pmd.h
> @@ -215,7 +215,8 @@ union acc100_dma_rsp_desc {
> timestampEn:1,
> iterCountFrac:8,
> iter_cnt:8,
> - rsrvd3:6,
> + harq_failure:1,
> + rsrvd3:5,
> sdone:1,
> fdone:1;
> uint32_t add_info_0;
> @@ -508,6 +509,8 @@ struct acc100_registry_addr {
> unsigned int depth_log1_offset;
> unsigned int qman_group_func;
> unsigned int ddr_range;
> + unsigned int pmon_ctrl_a;
> + unsigned int pmon_ctrl_b;
> };
>
> /* Structure holding registry addresses for PF */
> @@ -537,6 +540,8 @@ static const struct acc100_registry_addr pf_reg_addr = {
> .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
> .qman_group_func = HWPfQmgrGrpFunction0,
> .ddr_range = HWPfDmaVfDdrBaseRw,
> + .pmon_ctrl_a = HWPfPermonACntrlRegVf,
> + .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
> };
>
> /* Structure holding registry addresses for VF */
> @@ -566,6 +571,8 @@ static const struct acc100_registry_addr vf_reg_addr = {
> .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
> .qman_group_func = HWVfQmgrGrpFunction0Vf,
> .ddr_range = HWVfDmaDdrBaseRangeRoVf,
> + .pmon_ctrl_a = HWVfPmACntrlRegVf,
> + .pmon_ctrl_b = HWVfPmBCntrlRegVf,
> };
>
> /* Structure associated with each queue. */
> diff --git a/drivers/baseband/acc100/acc100_vf_enum.h b/drivers/baseband/acc100/acc100_vf_enum.h
> index b512af33fc..5807a9d0fd 100644
> --- a/drivers/baseband/acc100/acc100_vf_enum.h
> +++ b/drivers/baseband/acc100/acc100_vf_enum.h
> @@ -70,4 +70,10 @@ enum {
> ACC100_VF_INT_QMGR_AQ_OVERTHRESHOLD = 9,
> };
>
> +/* TIP PF2VF Comms */
> +enum {
> + ACC100_VF2PF_STATUS_REQUEST = 0,
> + ACC100_VF2PF_USING_VF = 1,
> +};
> +
> #endif /* ACC100_VF_ENUM_H */
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index ea54152856..9c15797503 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -292,6 +292,13 @@ fetch_acc100_config(struct rte_bbdev *dev)
> acc100_conf->q_dl_5g.aq_depth_log2);
> }
>
> +static inline void
> +acc100_vf2pf(struct acc100_device *d, unsigned int payload)
> +{
> + if (d->device_variant == ACC101_VARIANT)
> + acc100_reg_write(d, HWVfHiVfToPfDbellVf, payload);
> +}
> +
> static void
> free_base_addresses(void **base_addrs, int size)
> {
> @@ -646,6 +653,11 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
> /* Read the populated cfg from ACC100 registers */
> fetch_acc100_config(dev);
>
> + for (value = 0; value <= 2; value++) {
> + acc100_reg_write(d, reg_addr->pmon_ctrl_a, value);
> + acc100_reg_write(d, reg_addr->pmon_ctrl_b, value);
> + }
> +
> /* Release AXI from PF */
> if (d->pf_device)
> acc100_reg_write(d, HWPfDmaAxiControl, 1);
> @@ -712,6 +724,7 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
>
> /* Mark as configured properly */
> d->configured = true;
> + acc100_vf2pf(d, ACC100_VF2PF_USING_VF);
>
> rte_bbdev_log_debug(
> "ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#"
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
next prev parent reply other threads:[~2022-09-15 9:13 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-20 2:31 [PATCH v2 00/37] baseband/acc100: changes for 22.11 Hernan Vargas
2022-08-20 2:31 ` [PATCH v2 01/37] baseband/acc100: add enqueue status Hernan Vargas
2022-09-14 16:26 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 02/37] baseband/acc100: update ring availability calculation Hernan Vargas
2022-09-14 16:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 03/37] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-09-14 17:00 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 04/37] baseband/acc100: free SW ring mem for reconfiguration Hernan Vargas
2022-09-14 19:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 05/37] baseband/acc100: memory leak fix Hernan Vargas
2022-09-14 8:50 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 06/37] baseband/acc100: add default e value for FCW Hernan Vargas
2022-09-14 19:24 ` Maxime Coquelin
2022-09-15 11:00 ` Thomas Monjalon
2022-09-16 1:12 ` Chautru, Nicolas
2022-09-16 7:11 ` Thomas Monjalon
2022-08-20 2:31 ` [PATCH v2 07/37] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-09-14 19:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 08/37] baseband/acc100: add scatter-gather support Hernan Vargas
2022-09-14 20:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 09/37] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-09-14 20:16 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 10/37] baseband/acc100: avoid mux for small inbound frames Hernan Vargas
2022-09-14 20:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 11/37] baseband/acc100: separate validation functions from debug Hernan Vargas
2022-09-14 20:35 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 12/37] baseband/acc100: add LDPC transport block support Hernan Vargas
2022-09-14 20:47 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning Hernan Vargas
2022-09-15 7:37 ` Maxime Coquelin
2022-09-16 0:31 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 14/37] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-09-15 7:43 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 15/37] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-09-15 8:15 ` Maxime Coquelin
2022-09-16 1:20 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 16/37] baseband/acc100: add ring companion address Hernan Vargas
2022-09-15 9:09 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 17/37] baseband/acc100: configure PMON control registers Hernan Vargas
2022-09-15 9:12 ` Maxime Coquelin [this message]
2022-08-20 2:31 ` [PATCH v2 18/37] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-09-15 9:52 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 19/37] baseband/acc100: add queue stop operation Hernan Vargas
2022-09-15 9:55 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 20/37] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-09-15 10:01 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 21/37] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-09-15 10:02 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 23/37] baseband/acc100: update uplink CB input length Hernan Vargas
2022-09-15 10:12 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 24/37] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 25/37] baseband/acc100: update log messages Hernan Vargas
2022-09-15 10:14 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 26/37] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-09-15 10:15 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 27/37] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-09-15 10:18 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 28/37] baseband/acc100: make desc optimization optional Hernan Vargas
2022-09-15 10:19 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 29/37] baseband/acc100: update device info Hernan Vargas
2022-09-15 10:20 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 30/37] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-09-15 10:21 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 31/37] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-09-15 10:22 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 32/37] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-09-15 10:23 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 33/37] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-09-15 10:24 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 34/37] baseband/acc100: update meson file sdk dependency Hernan Vargas
2022-09-15 10:31 ` Maxime Coquelin
2022-09-15 10:57 ` Thomas Monjalon
2022-09-16 0:39 ` Chautru, Nicolas
2022-08-20 2:31 ` [PATCH v2 35/37] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 36/37] baseband/acc100: make HARQ layout memory 4GB Hernan Vargas
2022-09-15 11:33 ` Maxime Coquelin
2022-08-20 2:31 ` [PATCH v2 37/37] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-09-15 11:34 ` Maxime Coquelin
2022-08-23 15:59 ` [EXT] [PATCH v2 00/37] baseband/acc100: changes for 22.11 Akhil Goyal
2022-08-24 18:23 ` Chautru, Nicolas
2022-09-06 20:03 ` Chautru, Nicolas
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