From: "Rybalchenko, Kirill" <kirill.rybalchenko@intel.com>
To: "Xing, Beilei" <beilei.xing@intel.com>,
"Zhang, Qi Z" <qi.z.zhang@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] net/i40e: add log when setting input set
Date: Wed, 14 Mar 2018 15:46:49 +0000 [thread overview]
Message-ID: <696B43C21188DF4F9C9091AAE4789B824E2D65F4@IRSMSX108.ger.corp.intel.com> (raw)
In-Reply-To: <1518332150-85375-1-git-send-email-beilei.xing@intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Beilei Xing
> Sent: Sunday 11 February 2018 06:56
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/i40e: add log when setting input set
>
> This patch adds log when setting input set since global configuration is
> changed.
>
> Signed-off-by: Beilei Xing <beilei.xing@intel.com>
> ---
> drivers/net/i40e/rte_pmd_i40e.c | 30 +++++++++++++++++++++---------
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/i40e/rte_pmd_i40e.c
> b/drivers/net/i40e/rte_pmd_i40e.c index dae59e6..1288c51 100644
> --- a/drivers/net/i40e/rte_pmd_i40e.c
> +++ b/drivers/net/i40e/rte_pmd_i40e.c
> @@ -3071,6 +3071,7 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t
> pctype, {
> struct rte_eth_dev *dev;
> struct i40e_hw *hw;
> + struct i40e_pf *pf;
> uint64_t inset_reg;
> uint32_t mask_reg[2];
> int i;
> @@ -3086,6 +3087,12 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t
> pctype,
> return -EINVAL;
>
> hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> + pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
> +
> + if (pf->support_multi_driver) {
> + PMD_DRV_LOG(ERR, "Input set configuration is not
> supported.");
> + return -ENOTSUP;
> + }
>
> /* Clear mask first */
> for (i = 0; i < 2; i++)
> @@ -3098,14 +3105,17 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t
> pctype,
>
> switch (inset_type) {
> case INSET_HASH:
> - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0,
> pctype),
> - (uint32_t)(inset_reg & UINT32_MAX));
> - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1,
> pctype),
> - (uint32_t)((inset_reg >>
> - I40E_32_BIT_WIDTH) &
> UINT32_MAX));
> + i40e_check_write_global_reg(hw,
> I40E_GLQF_HASH_INSET(0, pctype),
> + (uint32_t)(inset_reg &
> UINT32_MAX));
> + i40e_check_write_global_reg(hw,
> I40E_GLQF_HASH_INSET(1, pctype),
> + (uint32_t)((inset_reg >>
> + I40E_32_BIT_WIDTH) &
> UINT32_MAX));
> for (i = 0; i < 2; i++)
> - i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i,
> pctype),
> - mask_reg[i]);
> + i40e_check_write_global_reg(hw,
> + I40E_GLQF_HASH_MSK(i,
> pctype),
> + mask_reg[i]);
> + i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
> + i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
> break;
> case INSET_FDIR:
> i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype,
> 0), @@ -3114,8 +3124,10 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t
> pctype,
> (uint32_t)((inset_reg >>
> I40E_32_BIT_WIDTH) &
> UINT32_MAX));
> for (i = 0; i < 2; i++)
> - i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i,
> pctype),
> - mask_reg[i]);
> + i40e_check_write_global_reg(hw,
> + I40E_GLQF_FD_MSK(i,
> pctype),
> + mask_reg[i]);
> + i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
> break;
> case INSET_FDIR_FLX:
> i40e_check_write_reg(hw,
> I40E_PRTQF_FD_FLXINSET(pctype),
> --
> 2.5.5
Reviewed-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
next prev parent reply other threads:[~2018-03-14 15:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-11 6:55 Beilei Xing
2018-03-14 15:46 ` Rybalchenko, Kirill [this message]
2018-03-28 1:16 ` Zhang, Qi Z
2018-03-29 5:47 ` Zhang, Helin
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