From: "Wu, Jingjing" <jingjing.wu@intel.com>
To: "Zhang, Helin" <helin.zhang@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Kenguva, Monica" <monica.kenguva@intel.com>,
"Murray, Steven J" <steven.j.murray@intel.com>,
"Nelson, Shannon" <shannon.nelson@intel.com>
Subject: Re: [dpdk-dev] [PATCH v2 03/33] i40e: adjustment of register definitions and relevant
Date: Fri, 8 May 2015 03:21:47 +0000 [thread overview]
Message-ID: <9BB6961774997848B5B42BEC655768F8C18318@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <1430406219-23901-4-git-send-email-helin.zhang@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
> -----Original Message-----
> From: Zhang, Helin
> Sent: Thursday, April 30, 2015 11:03 PM
> To: dev@dpdk.org
> Cc: Cao, Min; Xu, Qian Q; Wu, Jingjing; Liu, Jijiang; Kenguva, Monica; Patel,
> Rashmin N; Murray, Steven J; Nelson, Shannon; Zhang, Helin
> Subject: [PATCH v2 03/33] i40e: adjustment of register definitions and
> relevant
>
> Some macros of register definitions or relevant are added, modified or
> deleted. In detail, they are as follows.
> - I40E_PRTDCB_RUPTQ
> - I40E_GLGEN_GPIO_CTL
> - I40E_GLGEN_MDIO_CTRL
> - I40E_GLGEN_RSTENA_EMP
> - I40E_GLPCI_LATCT
> - I40E_GLTPH_CTRL
> - I40E_GLPRT_BPRCH
> - I40E_GLPRT_TDPC
> - I40E_GLSCD_QUANTA
> Also reading the register of I40E_GLPRT_TDPC is deleted as its definition is
> deleted.
>
> Signed-off-by: Helin Zhang <helin.zhang@intel.com>
> ---
> lib/librte_pmd_i40e/i40e/i40e_register.h | 52 ++++++++++++++++------------
> ----
> lib/librte_pmd_i40e/i40e_ethdev.c | 3 --
> 2 files changed, 26 insertions(+), 29 deletions(-)
>
> v2 changes:
> Removed anything about Fortpark or FPGA as they shouldn't be there.
>
> diff --git a/lib/librte_pmd_i40e/i40e/i40e_register.h
> b/lib/librte_pmd_i40e/i40e/i40e_register.h
> index 888c3c3..c8a8d77 100644
> --- a/lib/librte_pmd_i40e/i40e/i40e_register.h
> +++ b/lib/librte_pmd_i40e/i40e/i40e_register.h
> @@ -318,6 +318,10 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7,
> I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) #define
> I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 #define
> I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7,
> I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
> +#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /*
> _i=0...7 */ /* Reset: CORER */
> +#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7
> +#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 #define
> +I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF,
> +I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
> #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
> #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 #define
> I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF,
> I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) @@ -429,6 +433,8 @@ POSSIBILITY
> OF SUCH DAMAGE.
> #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1,
> I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
> #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 #define
> I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F,
> I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
> +#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26
> +#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF,
> I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
> #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
> #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 #define
> I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F,
> I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
> @@ -492,7 +498,9 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
> #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1,
> I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
> #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 -#define
> I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF,
> I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
> +#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK
> I40E_MASK(0x7FF,
> +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
> +#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29 #define
> +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7,
> +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
> #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4))
> /* _i=0...3 */ /* Reset: POR */
> #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
> #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 @@ -556,9
> +564,6 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F,
> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
> #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 #define
> I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1,
> I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
> -#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR
> */
> -#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 -#define
> I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1,
> I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
> #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
> #define I40E_GLGEN_RTRIG_CORER_SHIFT 0
> #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1,
> I40E_GLGEN_RTRIG_CORER_SHIFT)
> @@ -1074,7 +1079,7 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F,
> I40E_PFINT_RATEN_INTERVAL_SHIFT)
> #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 #define
> I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1,
> I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
> -#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */
> +#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER
> */
> #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 #define
> I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3,
> I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
> #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /*
> _i=0...1535 */ /* Reset: CORER */
> @@ -1179,7 +1184,7 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_VFINT_ITRN_MAX_INDEX 2
> #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 #define
> I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF,
> I40E_VFINT_ITRN_INTERVAL_SHIFT)
> -#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4))
> /* _i=0...127 */ /* Reset: VFR */
> +#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4))
> /* _i=0...127 */ /* Reset: CORER */
> #define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
> #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 #define
> I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3,
> I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
> @@ -1811,9 +1816,6 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
> #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 #define
> I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
> -#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */
> -#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 -#define
> I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
> #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
> #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
> #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1,
> I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
> @@ -1910,6 +1912,11 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1,
> I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
> #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 #define
> I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1,
> I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
> +#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */
> +#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9
> +#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3,
> I40E_GLTPH_CTRL_DESC_PH_SHIFT)
> +#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11
> +#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3,
> I40E_GLTPH_CTRL_DATA_PH_SHIFT)
> #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
> #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 #define
> I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7,
> I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
> @@ -2382,20 +2389,20 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
> #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> #define I40E_GLPRT_BPRCH_MAX_INDEX 3
> -#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
> -#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF,
> I40E_GLPRT_BPRCH_UPRCH_SHIFT)
> +#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0
> +#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF,
> +I40E_GLPRT_BPRCH_BPRCH_SHIFT)
> #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> #define I40E_GLPRT_BPRCL_MAX_INDEX 3
> -#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
> -#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPRT_BPRCL_UPRCH_SHIFT)
> +#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0
> +#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF,
> +I40E_GLPRT_BPRCL_BPRCL_SHIFT)
> #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> #define I40E_GLPRT_BPTCH_MAX_INDEX 3
> -#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
> -#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF,
> I40E_GLPRT_BPTCH_UPRCH_SHIFT)
> +#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0
> +#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF,
> +I40E_GLPRT_BPTCH_BPTCH_SHIFT)
> #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> #define I40E_GLPRT_BPTCL_MAX_INDEX 3
> -#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
> -#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPRT_BPTCL_UPRCH_SHIFT)
> +#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0
> +#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF,
> +I40E_GLPRT_BPTCL_BPTCL_SHIFT)
> #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /*
> _i=0...3 */ /* Reset: CORER */
> #define I40E_GLPRT_CRCERRS_MAX_INDEX 3
> #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 @@ -2628,10 +2635,6
> @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_GLPRT_TDOLD_MAX_INDEX 3
> #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 #define
> I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
> -#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> -#define I40E_GLPRT_TDPC_MAX_INDEX 3
> -#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
> -#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF,
> I40E_GLPRT_TDPC_TDPC_SHIFT)
> #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */
> /* Reset: CORER */
> #define I40E_GLPRT_UPRCH_MAX_INDEX 3
> #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
> @@ -2998,9 +3001,6 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
> #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 #define
> I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF,
> I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
> -#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */
> -#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 -#define
> I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7,
> I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
> #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
> #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 #define
> I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF,
> I40E_GL_MDET_RX_FUNCTION_SHIFT) @@ -3266,7 +3266,7 @@
> POSSIBILITY OF SUCH DAMAGE.
> #define I40E_VFINT_ITRN1_MAX_INDEX 2
> #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 #define
> I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF,
> I40E_VFINT_ITRN1_INTERVAL_SHIFT)
> -#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */
> +#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset:
> CORER */
> #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 #define
> I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3,
> I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
> #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */
> /* Reset: CORER */
> @@ -3374,4 +3374,4 @@ POSSIBILITY OF SUCH DAMAGE.
> #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1,
> I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
> #define I40E_VFQF_HREGION_REGION_7_SHIFT 29
> #define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7,
> I40E_VFQF_HREGION_REGION_7_SHIFT)
> -#endif
> +#endif /* _I40E_REGISTER_H_ */
> diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c
> b/lib/librte_pmd_i40e/i40e_ethdev.c
> index 49d1067..3d45429 100644
> --- a/lib/librte_pmd_i40e/i40e_ethdev.c
> +++ b/lib/librte_pmd_i40e/i40e_ethdev.c
> @@ -1269,9 +1269,6 @@ i40e_dev_stats_get(struct rte_eth_dev *dev,
> struct rte_eth_stats *stats)
> I40E_GLPRT_BPTCL(hw->port),
> pf->offset_loaded, &os->eth.tx_broadcast,
> &ns->eth.tx_broadcast);
> - i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
> - pf->offset_loaded, &os->eth.tx_discards,
> - &ns->eth.tx_discards);
> /* GLPRT_TEPC not supported */
>
> /* additional port specific stats */
> --
> 1.8.1.4
next prev parent reply other threads:[~2015-05-08 3:21 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-20 8:22 [dpdk-dev] [PATCH 00/18] i40e base driver update Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 01/18] i40e: copyright update Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 02/18] i40e: disable setting phy configuration Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 03/18] i40e: adjustment of register definitions and relevant Helin Zhang
2015-04-27 17:16 ` Thomas Monjalon
2015-04-28 2:29 ` Zhang, Helin
2015-04-20 8:22 ` [dpdk-dev] [PATCH 04/18] i40e: support of CEE DCBX on recent firmware versions Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 05/18] i40e: rework of 'i40e_hmc_get_object_va' Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 06/18] i40e: support of Fortpark device IDs and mac types Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 07/18] i40e: rename 'err' to 'perrno' Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 08/18] i40e: support NVM read on Fortpark, with minor enhancements Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 09/18] i40e: adminq enhancements Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 10/18] i40e: support of firmware build number Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 11/18] i40e: support of building both PF and VF driver together Helin Zhang
2015-04-27 17:25 ` Thomas Monjalon
2015-04-28 2:33 ` Zhang, Helin
2015-04-20 8:22 ` [dpdk-dev] [PATCH 12/18] i40e: enhancements of AQ commands and common interfaces Helin Zhang
2015-04-27 17:26 ` Thomas Monjalon
2015-04-28 2:34 ` Zhang, Helin
2015-04-20 8:22 ` [dpdk-dev] [PATCH 13/18] i40e: replacement of 'i40e_debug_read_register()' Helin Zhang
2015-04-27 17:28 ` Thomas Monjalon
2015-04-28 2:34 ` Zhang, Helin
2015-04-20 8:22 ` [dpdk-dev] [PATCH 14/18] i40e: add new interfaces of AQ commands and relevant Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 15/18] i40e: support of Fortpark FPGA Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 16/18] i40e: add more virtual channel operations Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 17/18] i40e: support of structure and command length check Helin Zhang
2015-04-20 8:22 ` [dpdk-dev] [PATCH 18/18] i40e: Minor enhancements in i40e_type.h Helin Zhang
2015-04-22 7:26 ` [dpdk-dev] [PATCH 00/18] i40e base driver update Cao, Min
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 00/33] " Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 01/33] i40e: copyright update Helin Zhang
2015-05-08 3:22 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 02/33] i40e: disable setting of phy configuration Helin Zhang
2015-05-08 3:22 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 03/33] i40e: adjustment of register definitions and relevant Helin Zhang
2015-05-08 3:21 ` Wu, Jingjing [this message]
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 04/33] i40e/base: rename 'err' to 'perrno' Helin Zhang
2015-05-08 3:20 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 05/33] i40e/base: support of building both PF and VF driver together Helin Zhang
2015-05-08 3:25 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 06/33] i40e/base: support of CEE DCBX on recent firmware versions Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 07/33] i40e: replacement of 'i40e_debug_read_register()' Helin Zhang
2015-05-08 3:23 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 08/33] i40e/base: rework of 'i40e_hmc_get_object_va' Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 09/33] i40e/base: update of shadow RAM read/write functions Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 10/33] i40e/base: catch NVM write semaphore timeout and retry Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 11/33] i40e/base: check for AQ timeout in aq_rc decode Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 12/33] i40e/base: fix up NVM update sm error handling Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 13/33] i40e/base: enhancement of polling NVM semaphore Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 14/33] i40e/base: enhancements of NVM checksum calculation Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 15/33] i40e/base: replacement of DEBUGOUT() with i40e_debug() Helin Zhang
2015-05-08 3:24 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 16/33] i40e/base: add fw build info to AQ data Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 17/33] i40e/base: define and use i40e_is_vf() Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 18/33] i40e/base: grab NVM devstarter version not image version Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 19/33] i40e/base: enhancements on adminq init and sending asq command Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 20/33] i40e/base: i40e_aq_get_link_info() should be used directly Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 21/33] i40e/base: add new interfaces for future use Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 22/33] i40e/base: update of get/set LED functions Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 23/33] i40e/base: clean up sparse complaint in i40e_debug_aq Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 24/33] i40e/base: get pf_id from HW rather than PCI function Helin Zhang
2015-05-08 3:20 ` Wu, Jingjing
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 25/33] i40e/base: find partition_id in npar mode, and disable FCOE by default Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 26/33] i40e/base: Reassign incorrect PHY type as a workaround for a FW issue Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 27/33] i40e/base: add AOC phy types to case statement in get_media_type Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 28/33] i40e/base: support for iSCSI capability Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 29/33] i40e/base: set FLAG_RD when sending driver version to FW Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 30/33] i40e/base: future proof some sizeof calls Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 31/33] i40e/base: add more virtual channel operations for future use Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 32/33] i40e/base: rework of structures and macros " Helin Zhang
2015-04-30 15:03 ` [dpdk-dev] [PATCH v2 33/33] i40e/base: modifications " Helin Zhang
2015-05-07 1:17 ` [dpdk-dev] [PATCH v2 00/33] i40e base driver update Cao, Min
2015-05-08 5:54 ` Liu, Jijiang
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